View PIC12F184012_7358787.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 2011-2012 microchip technology inc. ds41441c-page 1 high-performance risc cpu: ? only 49 instructions to learn: - all single-cycle instructions except branches ? operating speed: - dc ? 32 mhz oscillator/clock input - dc ? 125 ns instruction cycle ? interrupt capability with automatic context saving ? 16-level deep hardware stack with optional overflow/underflow reset ? direct, indirect and relative addressing modes: - two full 16-bit file select registers (fsrs) - fsrs can read program and data memory flexible oscillator structure: ? precision 32 mhz internal oscillator block: - factory calibrated to 1%, typical - software selectable frequencies range of 31 khz to 32 mhz ? 31 khz low-power internal oscillator ? four crystal modes up to 32 mhz ? three external clock modes up to 32 mhz ? 4x phase lock loop (pll) ? fail-safe clock monitor: - allows for safe shutdown if peripheral clock stops ? two-speed oscillator start-up ? reference clock module: - programmable clock output frequency and duty-cycle special microcontroller features: ? operating voltage range: - 2.3v-5.5v (pic12f1840) - 1.8v-3.6v (pic12lf1840) ? self-reprogrammable under software control ? power-on reset (por), power-up timer (pwrt) and oscillator start-up timer (ost) ? programmable brown-out reset (bor) ? extended watchdog timer (wdt) ? in-circuit serial programming? (icsp?) via two pins ? in-circuit debug (icd) via two pins ? enhanced low-voltage programming (lvp) ? programmable code protection ? power-saving sleep mode extreme low-power management with pic12lf1840 xlp: ? sleep mode: 20 na @ 1.8v, typical ? watchdog timer: 500 na @ 1.8v, typical ? timer1 oscillator: 300 na @ 32 khz, 1.8v, typical ? operating current: 30 ? a/mhz @ 1.8v, typical analog features: ? analog-to-digital converter (adc) module: - 10-bit resolution, 4 channels - conversion available during sleep ? analog comparator module: - one rail-to-rail analog comparator - power mode control - software controllable hysteresis ? voltage reference module: - fixed voltage reference (fvr) with 1.024v, 2.048v and 4.096v output levels - 5-bit rail-to-rail resistive dac with positive and negative reference selection peripheral highlights: ? 5 i/o pins and 1 input only pin: - high current sink/source 25 ma/25 ma - programmable weak pull-ups - programmable interrupt-on-change pins ? timer0: 8-bit timer/counter with 8-bit prescaler ? enhanced timer1: - 16-bit timer/counter with prescaler - external gate input mode - dedicated, low-power 32 khz oscillator driver ? timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler ? enhanced ccp (eccp) module: - software selectable time bases - auto-shutdown and auto-restart - pwm steering ? master synchronous serial port (mssp) with spi and i 2 c tm with: - 7-bit address masking - smbus/pmbus tm compatibility ? enhanced universal synchronous asynchronous receiver transmitter (eusart) module: - rs-232, rs-485 and lin compatible - auto-baud detect ? capacitive sensing (cps) module (mtouch tm ): - 4 input channels pic12(l)f1840 8-pin flash microcontrollers with xlp technology
pic12(l)f1840 ds41441c-page 2 ? 2011-2012 microchip technology inc. peripheral features (continued): ? data signal modulator module: - selectable modulator and carrier sources ?sr latch: - multiple set/reset input options - emulates 555 timer applications pic12(l)f1822/1840/pic16(l)f182x/1847 family types device data sheet index program memory flash (words) data eeprom (bytes) data sram (bytes) i/o?s (2) 10-bit adc (ch) capsense (ch) comparators timers (8/16-bit) eusart mssp (i 2 c?/spi) eccp (full-bridge) eccp (half-bridge) ccp sr latch debug (1) xlp pic12(l)f1822 (1) 2k 256 128 6 4 4 1 2/1 1 1 0/1/0 y i/h y pic12(l)f1840 (2) 4k 256 256 6 4 4 1 2/1 1 1 0/1/0 y i/h y pic16(l)f1823 (1) 2k 256 128 12 8 8 2 2/1 1 1 1/0/0 y i/h y pic16(l)f1824 (3) 4k 256 256 12 8 8 2 4/1 1 1 1/1/2 y i/h y pic16(l)f1825 (4) 8k 256 1024 12 8 8 2 4/1 1 1 1/1/2 y i/h y pic16(l)f1826 (5) 2k 256 256 16 12 12 2 2/1 1 1 1/0/0 y i/h y pic16(l)f1827 (5) 4k 256 384 16 12 12 2 4/1 1 2 1/1/2 y i/h y pic16(l)f1828 (3) 4k 256 256 18 12 12 2 4/1 1 1 1/1/2 y i/h y pic16(l)f1829 (4) 8k 256 1024 18 12 12 2 4/1 1 2 1/1/2 y i/h y pic16(l)f1847 (6) 8k 256 1024 16 12 12 2 4/1 1 2 1/1/2 y i/h y note 1: i - debugging, integrated on chip; h - debugging, available using debug header. 2: one pin is input-only. data sheet index: (unshaded devices are described in this document.) 1: ds41413 pic12(l)f1822/pic16(l)f1823 data sheet, 8/14-pin flash microcontrollers. 2: ds41441 pic12(l)f1840 data sheet, 8-pin flash microcontrollers. 3: ds41419 pic16(l)f1824/1828 data sheet, 28/40/44-pin flash microcontrollers. 4: ds41440 pic16(l)f1825/1829 data sheet, 14/20-pin flash microcontrollers. 5: ds41391 pic16(l)f1826/1827 data sheet, 18/20/28-pin flash microcontrollers. 6: ds41453 pic16(l)f1847 data sheet, 18/20/28-pin flash microcontrollers. note: for other small form-factor package availibility and marking information, please visit http://www.microchip.com/packaging or contact your local sales office.
? 2011-2012 microchip technology inc. ds41441c-page 3 pic12(l)f1840 figure 1: 8-pin diagram for pic12(l)f1840 table 1: 8-pin allocatio n table (pic12(l)f1840) i/o 8-pin pdip/soic/dfn adc reference cap sense comparator sr latch timers eccp eusart mssp interrupt modulator pull-up basic ra0 7 an0 dacout cps0 c1in+ ? ? p1b tx ck sdo ss (1) ioc mdout y icspdat icddat ra1 6 an1 v ref cps1 c1in0- sri ? ? rx dt scl sck ioc mdmin yicspclk icpclk ra2 5 an2 ? cps2 c1out srq t0cki ccp1 p1a flt0 ? sda sdi int/ ioc mdcin1 y ? ra34?? ?? ?t1g (1) ?? ss ioc ? y mclr v pp ra4 3 an3 ? cps3 c1in1- ? t1g t1oso p1b (1) tx (1) ck (1) sdo (1) ioc mdcin2 y osc2 clkout clkr ra5 2 ? ? ? ? srnq t1cki t1osi ccp1 (1) p1a (1) rx (1) dt (1) ?ioc? yosc1 clkin v dd 1 ? ? ? ? ? ? ? ? ? ? ? ? v dd v ss 8??????????? ?v ss note 1: alternate pin function selected with the apfcon ( register 12-1 ) register. pdip, soic, dfn 1 2 3 4 8 7 6 5 v dd ra5 ra4 mclr /v pp /ra3 v ss ra0/icspdat ra1/icspclk ra2 note 1: see ta b l e 1 for the location of all peripheral functions. pic12(l)f1840
pic12(l)f1840 ds41441c-page 4 ? 2011-2012 microchip technology inc. table of contents 1.0 device overview ............................................................................................................. ............................................................. 7 2.0 enhanced mid-range cpu ...................................................................................................... .................................................. 11 3.0 memory organization ......................................................................................................... ........................................................ 13 4.0 device configuration ........................................................................................................ .......................................................... 33 5.0 oscillator module (with fail-safe clock monitor)............................................................................ ........................................... 39 6.0 reference clock module ...................................................................................................... ...................................................... 57 7.0 resets ...................................................................................................................... .................................................................. 61 8.0 interrupts .................................................................................................................. .................................................................. 69 9.0 power-down mode (sleep) ..................................................................................................... ................................................... 79 10.0 watchdog timer (wdt) ....................................................................................................... ...................................................... 83 11.0 data eeprom and flash program memory control ............................................................................... .................................. 87 12.0 i/o ports .................................................................................................................. ................................................................. 101 13.0 interrupt-on-change ........................................................................................................ ......................................................... 109 14.0 fixed voltage reference (fvr) .............................................................................................. ................................................. 113 15.0 temperature indicator ...................................................................................................... ........................................................ 117 16.0 analog-to-digital converter (adc) module ................................................................................... ........................................... 119 17.0 digital-to-analog converter (dac) module ................................................................................... ........................................... 133 18.0 sr latch................................................................................................................... ................................................................ 137 19.0 comparator module.......................................................................................................... ........................................................ 141 20.0 timer0 module .............................................................................................................. ........................................................... 149 21.0 timer1 module .............................................................................................................. ........................................................... 153 22.0 timer2 modules............................................................................................................. ........................................................... 165 23.0 data signal modulator (dsm) ................................................................................................ .................................................. 169 24.0 capture/compare/pwm module ................................................................................................. ............................................. 179 25.0 master synchronous serial port (mssp) module ............................................................................... ..................................... 201 26.0 enhanced universal synchronous asynchronous receiver transmitter (eusart) .................................................. ............. 257 27.0 capacitive sensing (cps) module ............................................................................................ ............................................... 287 28.0 in-circuit serial programming ? (icsp ? ) .............................................................................................................................. .. 295 29.0 instruction set summary .................................................................................................... ...................................................... 299 30.0 electrical specifications.................................................................................................. .......................................................... 313 31.0 dc and ac characteristics graphs and tables ................................................................................ ....................................... 345 32.0 development support........................................................................................................ ....................................................... 383 33.0 packaging information...................................................................................................... ........................................................ 387 appendix a: revision history................................................................................................... .......................................................... 397 appendix b: device differences................................................................................................. ........................................................ 397 index .......................................................................................................................... ........................................................................ 399 the microchip web site ......................................................................................................... ............................................................ 405 customer change notification service ........................................................................................... ................................................... 405 customer support ............................................................................................................... ............................................................... 405 reader response ................................................................................................................ .............................................................. 406 product identification system.................................................................................................. ........................................................... 407
? 2011-2012 microchip technology inc. ds41441c-page 5 pic12(l)f1840 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please specify which device, re vision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
pic12(l)f1840 ds41441c-page 6 ? 2011-2012 microchip technology inc. notes:
? 2011-2012 microchip technology inc. ds41441c-page 7 pic12(l)f1840 1.0 device overview the pic12(l)f1840 are described within this data sheet. they are available in 8-pin packages. figure 1-1 shows a block diagram of the pic12(l)f1840 devices. ta b l e 1 - 2 shows the pinout descriptions. reference tab l e 1 - 1 for peripherals available per device. table 1-1: device peripheral summary peripheral pic12(l)f1840 adc capacitive sensing (cps) module data eeprom digital-to-analog converter (dac) digital signal modulator (dsm) eusart fixed voltage reference (fvr) sr latch capture/compare/pwm modules eccp1 comparators c1 master synchronous serial ports mssp timers timer0 timer1 timer2
pic12(l)f1840 ds41441c-page 8 ? 2011-2012 microchip technology inc. figure 1-1: pic12(l)f1840 block diagram porta eusart comparators mssp timer1 timer0 eccp1 adc 10-bit sr latch note 1: see applicable chapters for more information on peripherals. 2: see ta b l e 1 - 1 for peripherals available on specific devices. cpu program flash memory eeprom ram timing generation intrc oscillator mclr ( figure 2-1 ) modulator capsense clock clkr reference dac fvr osc1/clkin osc2/clkout
? 2011-2012 microchip technology inc. ds41441c-page 9 pic12(l)f1840 table 1-2: pic12(l)f1840 pinout description name function input type output type description ra0/an0/cps0/c1in+/ dacout/tx/ck/sdo/ ss (1) /p1b/mdout/icspdat/ icddat ra0 ttl cmos general purpose i/o. an0 an ? adc channel 0 input. cps0 an ? capacitive sensing input 0. c1in+ an ? comparator c1 positive input. dacout ? an digital-to-analog converter output. tx ? cmos usart asynchronous transmit. ck st cmos usart synchronous clock. sdo ? cmos spi data output. ss st ? slave select input. p1b ? cmos pwm output. mdout ? cmos modulator output. icspdat st cmos icsp? data i/o. ra1/an1/cps1/v ref /c1in0-/ sri/rx/dt/scl/sck/ mdmin/icspclk/icdclk ra1 ttl cmos general purpose i/o. an1 an ? adc channel 1 input. cps1 an ? capacitive sensing input 1. v ref an ? adc and dac positive voltage reference input. c1in0- an ? comparator c1 negative input. sri st ? sr latch input. rx st ? usart asynchronous input. dt st cmos usart synchronous data. scl i 2 c? od i 2 c? clock. sck st cmos spi clock. mdmin st ? modulator source input. icspclk st ? serial programming clock. ra2/an2/cps2/c1out/srq/ t0cki/ccp1/p1a/flt0/ sda/sdi/int/mdcin1 ra2 st cmos general purpose i/o. an2 an ? adc channel 2 input. cps2 an ? capacitive sensing input 2. c1out ? cmos comparator c1 output. srq ? cmos sr latch non-inverting output. t0cki st ? timer0 clock input. ccp1 st cmos capture/compare/pwm 1. p1a ? cmos pwm output. flt0 st ? eccp auto-shutdown fault input. sda i 2 c? od i 2 c? data input/output. sdi cmos ? spi data input. int st ? external interrupt. mdcin1 st ? modulator carrier input 1. ra3/ss /t1g (1) /v pp /mclr ra3 ttl ? general purpose input. ss st ? slave select input. t1g st ? timer1 gate input. v pp hv ? programming voltage. mclr st ? master clear with internal pull-up. legend: an = analog input or output cmos = cmos compatible input or output od = open drain ttl = ttl compatible input st = schmitt trigger input with cmos levels i 2 c? = schmitt trigger input with i 2 c hv = high voltage xtal = crystal levels note 1: alternate pin function selected with the apfcon ( register 12-1 ) register.
pic12(l)f1840 ds41441c-page 10 ? 2011-2012 microchip technology inc. ra4/an3/cps3/osc2/ clkout/t1oso/c1in1-/clkr/ sdo (1) /ck (1) /tx (1) /p1b (1) / t1g/mdcin2 ra4 ttl cmos general purpose i/o. an3 an ? adc channel 3 input. cps3 an ? capacitive sensing input 3. osc2 ? xtal crystal/resonator (lp, xt, hs modes). clkout ? cmos f osc /4 output. t1oso xtal xtal timer1 oscillator connection. c1in1- an ? comparator c1 negative input. clkr ? cmos clock reference output. sdo ? cmos spi data output. ck st cmos usart synchronous clock. tx ? cmos usart asynchronous transmit. p1b ? cmos pwm output. t1g st ? timer1 gate input. mdcin2 st ? modulator carrier input 2. ra5/clkin/osc1/t1osi/ t1cki/srnq/p1a (1) /ccp1 (1) / dt (1) /rx (1) ra5 ttl cmos general purpose i/o. clkin cmos ? external clock input (ec mode). osc1 xtal ? crystal/resonator (lp, xt, hs modes). t1osi xtal xtal timer1 oscillator connection. t1cki st ? timer1 clock input. srnq ? cmos sr latch inverting output. p1a ? cmos pwm output. ccp1 st cmos capture/compare/pwm 1. dt st cmos usart synchronous data. rx st ? usart asynchronous input. v dd v dd power ? positive supply. v ss v ss power ? ground reference. table 1-2: pic12(l)f1840 pinout description (continued) name function input type output type description legend: an = analog input or output cmos = cmos compatible input or output od = open drain ttl = ttl compatible input st = schmitt trigger input with cmos levels i 2 c? = schmitt trigger input with i 2 c hv = high voltage xtal = crystal levels note 1: alternate pin function selected with the apfcon ( register 12-1 ) register.
? 2011-2012 microchip technology inc. ds41441c-page 11 pic12(l)f1840 2.0 enhanced mid-range cpu this family of devices contain an enhanced mid-range 8-bit cpu core. the cpu has 49 instructions. interrupt capability includes automatic context saving. the hardware stack is 16 levels deep and has overflow and underflow reset capability. direct, indirect, and relative addressing modes are available. two file select registers (fsrs) provide the ability to read program and data memory. ? automatic interrupt context saving ? 16-level stack with overflow and underflow ? file select registers ? instruction set figure 2-1: core block diagram data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) direct addr 7 12 addr mux fsr reg status reg mux alu power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation osc1/clkin osc2/clkout v dd 8 8 brown-out reset 12 3 v ss internal oscillator block configuration data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) direct addr 7 addr mux fsr reg status reg mux alu w reg instruction decode & control timing generation v dd 8 8 3 v ss internal oscillator block configuration 15 data bus 8 14 program bus instruction reg program counter 16-level stack (15-bit) direct addr 7 ram addr addr mux indirect addr fsr0 reg status reg mux alu instruction decode and control timing generation v dd 8 8 3 v ss internal oscillator block configuration flash program memory ram fsr reg fsr reg fsr1 reg 15 15 mux 15 program memory read (pmr) 12 fsr reg fsr reg bsr reg 5
pic12(l)f1840 ds41441c-page 12 ? 2011-2012 microchip technology inc. 2.1 automatic interrupt context saving during interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. this saves stack space and user code. see section 8.5 ?automatic context saving? , for more information. 2.2 16-level stack with overflow and underflow these devices have an external stack memory 15 bits wide and 16 words deep. a stack overflow or under- flow will set the appropriate bit (stkovf or stkunf) in the pcon register, and if enabled will cause a soft- ware reset. see section 3.5 ?stack? for more details. 2.3 file select registers there are two 16-bit file select registers (fsr). fsrs can access all file registers and program memory, which allows one data pointer for all memory. when an fsr points to program memory, there is one additional instruction cycle in instructions using indf to allow the data to be fetched. general purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. there are also new instructions to support the fsrs. see section 3.6 ?indirect addressing? for more details. 2.4 instruction set there are 49 instructions for the enhanced mid-range cpu to support the features of the cpu. see section 29.0 ?instruction set summary? for more details.
? 2011-2012 microchip technology inc. ds41441c-page 13 pic12(l)f1840 3.0 memory organization these devices contain the following types of memory: ? program memory - configuration words - device id -user id - flash program memory ? data memory - core registers - special function registers - general purpose ram - common ram ? data eeprom memory (1) the following features are associated with access and control of program memory and data memory: ? pcl and pclath ?stack ? indirect addressing 3.1 program memory organization the enhanced mid-range core has a 15-bit program counter capable of addressing a 32k x 14 program memory space. table 3-1 shows the memory sizes implemented for the pic12(l)f1840 family. accessing a location above these boundaries will cause a wrap-around within the implemented memory space. the reset vector is at 0000h and the interrupt vector is at 0004h (see figure 3-1 ). note 1: the data eeprom memory and the method to access flash memory through the eecon registers is described in section 11.0 ?data eeprom and flash program memory control? . table 3-1: device sizes and addresses device program memory space (words) last program memory address pic12(l)f1840 4, 096 0fffh
pic12(l)f1840 ds41441c-page 14 ? 2011-2012 microchip technology inc. figure 3-1: program memory map and stack for pic12(l)f1840 3.1.1 reading program memory as data there are two methods of accessing constants in program memory. the first method is to use tables of retlw instructions. the second method is to set an fsr to point to the program memory. 3.1.1.1 retlw instruction the retlw instruction can be used to provide access to tables of constants. the recommended way to create such a table is shown in example 3-1 . example 3-1: retlw instruction the brw instruction makes this type of table very simple to implement. if your code must remain portable with previous generations of microcontrollers, then the brw instruction is not available so the older table read method must be used. pc<14:0> 15 0000h 0004h stack level 0 stack level 15 reset vector interrupt vector call, callw return, retlw stack level 1 0005h on-chip program memory page 0 07ffh rollover to page 0 0800h 0fffh 1000h 7fffh page 1 rollover to page 1 interrupt , retfie constants brw ;add index in w to ;program counter to ;select data retlw data0 ;index0 data retlw data1 ;index1 data retlw data2 retlw data3 my_function ;? lots of code? movlw data_index call constants ;? the constant is in w
? 2011-2012 microchip technology inc. ds41441c-page 15 pic12(l)f1840 3.1.1.2 indirect read with fsr the program memory can be accessed as data by set- ting bit 7 of the fsrxh register and reading the match- ing indfx register. the moviw instruction will place the lower 8 bits of the addressed word in the w register. writes to the program memory cannot be performed via the indf registers. instructions that access the pro- gram memory via the fsr require one extra instruction cycle to complete. example 3-2 demonstrates access- ing the program memory via an fsr. the high directive will set bit<7> if a label points to a location in program memory. example 3-2: accessing program memory via fsr 3.2 data memory organization the data memory is partitioned in 32 memory banks with 128 bytes in a bank. each bank consists of ( figure 3-2 ): ? 12 core registers ? 20 special function registers (sfr) ? up to 80 bytes of general purpose ram (gpr) ? 16 bytes of common ram the active bank is selected by writing the bank number into the bank select register (bsr). unimplemented memory will read as ? 0 ?. all data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two file select registers (fsr). see section 3.6 ?indirect addressing? for more information. 3.2.1 core registers the core registers contain the registers that directly affect the basic operation. the core registers occupy the first 12 addresses of every data memory bank (addresses x00h/x08h through x0bh/x8bh). these registers are listed below in ta b l e 3 - 2 . for detailed information, see tab l e 3 - 5 . table 3-2: core registers constants retlw data0 ;index0 data retlw data1 ;index1 data retlw data2 retlw data3 my_function ;? lots of code? movlw low constants movwf fsr1l movlw high constants movwf fsr1h moviw 0[fsr1] ;the program memory is in w addresses bankx x00h or x80h indf0 x01h or x81h indf1 x02h or x82h pcl x03h or x83h status x04h or x84h fsr0l x05h or x85h fsr0h x06h or x86h fsr1l x07h or x87h fsr1h x08h or x88h bsr x09h or x89h wreg x0ah or x8ah pclath x0bh or x8bh intcon
pic12(l)f1840 ds41441c-page 16 ? 2011-2012 microchip technology inc. 3.2.1.1 status register the status register, shown in register 3-1 , contains: ? the arithmetic status of the alu ? the reset status the status register can be the destination for any instruction, like any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper three bits and set the z bit. this leaves the status register as ? 000u u1uu ? (where u = unchanged). it is recommended, therefore, that only bcf, bsf, swapf and movwf instructions are used to alter the status register, because these instructions do not affect any status bits. for other instructions not affecting any status bits (refer to section 29.0 ?instruction set summary? ). 3.3 register definitions: status note 1: the c and dc bits operate as borrow and digit borrow out bits, respectively, in subtraction. register 3-1: status: status register u-0 u-0 u-0 r-1/q r-1/q r/w-0/u r/w-0/u r/w-0/u ? ? ? to pd zdc (1) c (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared q = value depends on condition bit 7-5 unimplemented: read as ? 0 ? bit 4 to : time-out bit 1 = after power-up, clrwdt instruction or sleep instruction 0 = a wdt time-out occurred bit 3 pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2 z: zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc: digit carry/digit borrow bit ( addwf , addlw , sublw , subwf instructions) (1) 1 = a carry-out from the 4th low-order bit of the result occurred 0 = no carry-out from the 4th low-order bit of the result bit 0 c: carry/borrow bit (1) ( addwf , addlw , sublw , subwf instructions) (1) 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note 1: for borrow , the polarity is reversed. a subtraction is executed by adding the two?s complement of the second operand.
? 2011-2012 microchip technology inc. ds41441c-page 17 pic12(l)f1840 3.3.1 special function register the special function registers are registers used by the application to control the desired operation of peripheral functions in the device. the special function registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0ch/x8ch through x1fh/x9fh). the registers associated with the operation of the peripherals are described in the appro- priate peripheral chapter of this data sheet. 3.3.2 general purpose ram there are up to 80 bytes of gpr in each data memory bank. the special function registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0ch/x8ch through x1fh/x9fh). 3.3.2.1 linear access to gpr the general purpose ram can be accessed in a non-banked method via the fsrs. this can simplify access to large memory structures. see section 3.6.2 ?linear data memory? for more information. 3.3.3 common ram there are 16 bytes of common ram accessible from all banks. figure 3-2: banked memory partitioning 3.3.4 device memory maps the memory maps for the device family are as shown in table 3-3 . 0bh 0ch 1fh 20h 6fh 70h 7fh 00h common ram (16 bytes) general purpose ram (80 bytes maximum) core registers (12 bytes) special function registers (20 bytes maximum) memory region 7-bit bank offset
pic12(l)f1840 ds41441c-page 18 ? 2011-2012 microchip technology inc. table 3-3: pic12(l)f1840 memory map, banks 0-7 legend: = unimplemented data memory locations, read as ? 0 ?. note 1: available only on pic12f1840. bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 000h core registers ( ta b l e 3 - 2 ) 080h core registers ( ta b l e 3 - 2 ) 100h core registers ( table 3-2 ) 180h core registers ( table 3-2 ) 200h core registers ( table 3-2 ) 280h core registers ( table 3-2 ) 300h core registers ( table 3-2 ) 380h core registers ( table 3-2 ) 00bh 08bh 10bh 18bh 20bh 28bh 30bh 38bh 00ch porta 08ch trisa 10ch lata 18ch ansela 20ch wpua 28ch ? 30ch ? 38ch ? 00dh ? 08dh ? 10dh ? 18dh ? 20dh ? 28dh ? 30dh ? 38dh ? 00eh ?08eh ?10eh ?18eh ?20eh ?28eh ?30eh ?38eh ? 00fh ?08fh ?10fh ?18fh ?20fh ?28fh ?30fh ?38fh ? 010h ?090h ?110h ?190h ?210h ?290h ? 310h ? 390h ? 011h pir1 091h pie1 111h cm1con0 191h eeadrl 211h sspbuf 291h ccpr1l 311h ? 391h iocap 012h pir2 092h pie2 112h cm1con1 192h eeadrh 212h sspadd 292h ccpr1h 312h ? 392h iocan 013h ?093h ?113h ? 193h eedatl 213h sspmask 293h ccp1con 313h ? 393h iocaf 014h ?094h ?114h ? 194h eedath 214h sspstat 294h pwm1con 314h ? 394h ? 015h tmr0 095h option_reg 115h cmout 195h eecon1 215h sspcon 295h ccp1as 315h ? 395h ? 016h tmr1l 096h pcon 116h borcon 196h eecon2 216h sspcon2 296h pstr1con 316h ? 396h ? 017h tmr1h 097h wdtcon 117h fvrcon 197h vregcon (1) 217h sspcon3 297h ? 317h ? 397h ? 018h t1con 098h osctune 118h daccon0 198h ?218h ?298h ? 318h ? 398h ? 019h t1gcon 099h osccon 119h daccon1 199h rcreg 219h ? 299h ? 319h ? 399h ? 01ah tmr2 09ah oscstat 11ah srcon0 19ah txreg 21ah ? 29ah ? 31ah ? 39ah clkrcon 01bh pr2 09bh adresl 11bh srcon1 19bh spbrgl 21bh ? 29bh ? 31bh ?39bh ? 01ch t2con 09ch adresh 11ch ? 19ch spbrgh 21ch ? 29ch ? 31ch ? 39ch mdcon 01dh ? 09dh adcon0 11dh apfcon 19dh rcsta 21dh ? 29dh ? 31dh ? 39dh mdsrc 01eh cpscon0 09eh adcon1 11eh ? 19eh txsta 21eh ?29eh ?31eh ? 39eh mdcarl 01fh cpscon1 09fh ?11fh ? 19fh baudcon 21fh ?29fh ?31fh ?39fh mdcarh 020h general purpose register 80 bytes 0a0h general purpose register 80 bytes 120h general purpose register 80 bytes 1a0h unimplemented read as ? 0 ? 220h unimplemented read as ? 0 ? 2a0h unimplemented read as ? 0 ? 320h unimplemented read as ? 0 ? 3a0h unimplemented read as ? 0 ? 06fh 0efh 16fh 1efh 26fh 2efh 36fh 3efh 070h common ram 0f0h accesses 70h ? 7fh 170h accesses 70h ? 7fh 1f0h accesses 70h ? 7fh 270h accesses 70h ? 7fh 2f0h accesses 70h ? 7fh 370h accesses 70h ? 7fh 3f0h accesses 70h ? 7fh 07fh 0ffh 17fh 1ffh 27fh 2ffh 37fh 3ffh
? 2011-2012 microchip technology inc. ds41441c-page 19 pic12(l)f1840 table 3-3: pic12(l)f1840 memory map (continued) bank 8 bank 9 bank 10 bank 11 bank 12 bank 13 bank 14 bank 15 400h 40bh core registers ( ta b l e 3 - 2 ) 480h 48bh core registers ( ta b l e 3 - 2 ) 500h 50bh core registers ( ta b l e 3 - 2 ) 580h 58bh core registers ( ta b l e 3 - 2 ) 600h 60bh core registers ( ta b l e 3 - 2 ) 680h 68bh core registers ( ta b l e 3 - 2 ) 700h 70bh core registers ( ta b l e 3 - 2 ) 780h 78bh core registers ( ta b l e 3 - 2 ) 40ch unimplemented read as ?0? 48ch unimplemented read as ?0? 50ch unimplemented read as ?0? 58ch unimplemented read as ?0? 60ch unimplemented read as ?0? 68ch unimplemented read as ?0? 70ch unimplemented read as ?0? 78ch unimplemented read as ?0? 46fh 4efh 56fh 5efh 66fh 6efh 76fh 7efh 470h common ram (accesses 70h ? 7fh) 4f0h common ram (accesses 70h ? 7fh) 570h common ram (accesses 70h ? 7fh) 5f0h common ram (accesses 70h ? 7fh) 670h common ram (accesses 70h ? 7fh) 6f0h common ram (accesses 70h ? 7fh) 770h common ram (accesses 70h ? 7fh) 7f0h common ram (accesses 70h ? 7fh) 47fh 4ffh 57fh 5ffh 67fh 6ffh 77fh 7ffh bank 16 bank 17 bank 18 bank 19 bank 20 bank 21 bank 22 bank 23 800h 80bh core registers ( ta b l e 3 - 2 ) 880h 88bh core registers ( ta b l e 3 - 2 ) 900h 90bh core registers ( ta b l e 3 - 2 ) 980h 98bh core registers ( ta b l e 3 - 2 ) a00h a0bh core registers ( ta b l e 3 - 2 ) a80h a8bh core registers ( ta b l e 3 - 2 ) b00h b0bh core registers ( ta b l e 3 - 2 ) b80h b8bh core registers ( ta b l e 3 - 2 ) 80ch unimplemented read as ?0? 88ch unimplemented read as ?0? 90ch unimplemented read as ?0? 98ch unimplemented read as ?0? a0ch unimplemented read as ?0? a8ch unimplemented read as ?0? b0ch unimplemented read as ?0? b8ch unimplemented read as ?0? 86fh 8efh 96fh 9efh a6fh aefh b6fh befh 870h common ram (accesses 70h ? 7fh) 8f0h common ram (accesses 70h ? 7fh) 970h common ram (accesses 70h ? 7fh) 9f0h common ram (accesses 70h ? 7fh) a70h common ram (accesses 70h ? 7fh) af0h common ram (accesses 70h ? 7fh) b70h common ram (accesses 70h ? 7fh) bf0h common ram (accesses 70h ? 7fh) 87fh 8ffh 97fh 9ffh a7fh affh b7fh bffh legend: = unimplemented data memory locations, read as ?0? bank 24 bank 25 bank 26 bank 27 bank 28 bank 29 bank 30 c00h c0bh core registers ( ta b l e 3 - 2 ) c80h c8bh core registers ( ta b l e 3 - 2 ) d00h d0bh core registers ( ta b l e 3 - 2 ) d80h d8bh core registers ( ta b l e 3 - 2 ) e00h e0bh core registers ( ta b l e 3 - 2 ) e80h e8bh core registers ( ta b l e 3 - 2 ) f00h f0bh core registers ( ta b l e 3 - 2 ) c0ch c6fh unimplemented read as ?0? c8ch cefh unimplemented read as ?0? d0ch d6fh unimplemented read as ?0? d8ch defh unimplemented read as ?0? e0ch e6fh unimplemented read as ?0? e8ch eefh unimplemented read as ?0? f0ch f6fh unimplemented read as ?0? c70h common ram (accesses 70h ? 7fh) cf0h common ram (accesses 70h ? 7fh) d70h common ram (accesses 70h ? 7fh) df0h common ram (accesses 70h ? 7fh) e70h common ram (accesses 70h ? 7fh) ef0h common ram (accesses 70h ? 7fh) f70h common ram (accesses 70h ? 7fh) c7fh cffh d7fh dffh e7fh effh f7fh
pic12(l)f1840 ds41441c-page 20 ? 2011-2012 microchip technology inc. table 3-4: pic12(l)f1840 memory map, bank 31 legend: = unimplemented data memory locations, read as ? 0 ?. bank 31 fa0h fe3h unimplemented read as ? 0 ? fe4h status_shad fe5h wreg_shad fe6h bsr_shad fe7h pclath_shad fe8h fsr0l_shad fe9h fsr0h_shad feah fsr1l_shad febh fsr1h_shad fech ? fedh stkptr feeh tosl fefh tosh
? 2011-2012 microchip technology inc. ds41441c-page 21 pic12(l)f1840 3.3.5 core function registers summary the core function registers listed in ta bl e 3 - 5 can be addressed from any bank. table 3-5: core funct ion registers summary addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets bank 0-31 x00h or x80h indf0 addressing this location uses contents of fsr0h/fsr0l to address data memory (not a physical register) xxxx xxxx uuuu uuuu x01h or x81h indf1 addressing this location uses contents of fsr1h/fsr1l to address data memory (not a physical register) xxxx xxxx uuuu uuuu x02h or x82h pcl program counter (pc) least significant byte 0000 0000 0000 0000 x03h or x83h status ? ? ?to pd zdcc ---1 1000 ---q quuu x04h or x84h fsr0l indirect data memory address 0 low pointer 0000 0000 uuuu uuuu x05h or x85h fsr0h indirect data memory address 0 high pointer 0000 0000 0000 0000 x06h or x86h fsr1l indirect data memory address 1 low pointer 0000 0000 uuuu uuuu x07h or x87h fsr1h indirect data memory address 1 high pointer 0000 0000 0000 0000 x08h or x88h bsr ? ? ? bsr4 bsr3 bsr2 bsr1 bsr0 ---0 0000 ---0 0000 x09h or x89h wreg working register 0000 0000 uuuu uuuu x0ah or x8ah pclath ? write buffer for the upper 7 bits of the program counter -000 0000 -000 0000 x0bh or x8bh intcon gie peie tmr0ie inte iocie tmr0if intf iocif 0000 0000 0000 0000 legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ? 0 ?, r = reserved. shaded locations are unimplemented, read as ? 0 ?.
pic12(l)f1840 ds41441c-page 22 ? 2011-2012 microchip technology inc. table 3-6: special function register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets bank 0 00ch porta ? ? ra5 ra4 ra3 ra2 ra1 ra0 --xx xxxx --xx xxxx 00dh to 010h ? unimplemented ? ? 011h pir1 tmr1gif adif rcif txif ssp1if ccp1if tmr2if tmr1if 0000 0000 0000 0000 012h pir2 osfif ? c1if eeif bcl1if ? ? ? 0-00 0--- 0-00 0--- 013h ? unimplemented ? ? 014h ? unimplemented ? ? 015h tmr0 timer0 module register xxxx xxxx uuuu uuuu 016h tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 017h tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 018h t1con tmr1cs1 tmr1cs0 t1ckps<1:0> t1oscen t1sync ?tmr1on 0000 00-0 uuuu uu-u 019h t1gcon tmr1ge t1gpol t1gtm t1gspm t1ggo/ done t1gval t1gss<1:0> 0000 0x00 uuuu uxuu 01ah tmr2 timer2 module register 0000 0000 0000 0000 01bh pr2 timer2 period register 1111 1111 1111 1111 01ch t2con ? t2outps<3:0> tmr2on t2ckps<1:0> -000 0000 -000 0000 01dh ? unimplemented ? ? 01eh cpscon0 cpson cpsrm ? ? cpsrng<1:0> cpsout t0xcs 00-- 0000 00-- 0000 01fh cpscon1 ? ? ? ? ? ? cpsch<1:0> ---- --00 ---- --00 bank 1 08ch trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 --11 1111 --11 1111 08dh to 090h ? unimplemented ? ? 091h pie1 tmr1gie adie rcie txie ssp1ie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 092h pie2 osfie ? c1ie eeie bcl1ie ? ? ? 0-00 0--- 0-00 0--- 093h ? unimplemented ? ? 094h ? unimplemented ? ? 095h option_reg wpuen intedg tmr0cs tmr0se psa ps<2:0> 1111 1111 1111 1111 096h pcon stkovf stkunf ? ?rmclr ri por bor 00-- 11qq qq-- qquu 097h wdtcon ? ? wdtps<4:0> swdten --01 0110 --01 0110 098h osctune ? ? tun<5:0> --00 0000 --00 0000 099h osccon spllen ircf<3:0> ?scs<1:0> 0011 1-00 0011 1-00 09ah oscstat t1oscr pllr osts hfiofr hfiofl mfiofr lfiofr hfiofs 10q0 0q00 qqqq qq0q 09bh adresl adc result register low xxxx xxxx uuuu uuuu 09ch adresh adc result register high xxxx xxxx uuuu uuuu 09dh adcon0 ? chs<4:0> go/done adon -000 0000 -000 0000 09eh adcon1 adfm adcs<2:0> ? ? adpref<1:0> 0000 --00 0000 --00 09fh ? unimplemented ? ? legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: these registers can be addressed from any bank. 2: pic12f1840 only. 3: unimplemented, read as ? 1 ?.
? 2011-2012 microchip technology inc. ds41441c-page 23 pic12(l)f1840 bank 2 10ch lata ? ?lata5lata4 ?lata2lata1lata0 --xx -xxx --uu -uuu 10dh to 110h ? unimplemented ? ? 111h cm1con0 c1on c1out c1oe c1pol ? c1sp c1hys c1sync 0000 -100 0000 -100 112h cm1con1 c1intp c1intn c1pch<1:0> ? ? ? c1nch 0000 ---0 0000 ---0 113h ? unimplemented ? ? 114h ? unimplemented ? ? 115h cmout ? ? ? ? ? ? ?mc1out ---- ---0 ---- ---0 116h borcon sboren borfs ? ? ? ? ? borrdy 10-- ---q uu-- ---u 117h fvrcon fvren fvrrdy tsen tsrng cdafvr<1:0> adfvr<1:0> 0q00 0000 0q00 0000 118h daccon0 dacen daclps dacoe ? dacpss<1:0> ? ? 000- 00-- 000- 00-- 119h daccon1 ? ? ? dacr<4:0> ---0 0000 ---0 0000 11ah srcon0 srlen srclk<2:0> srqen srnqen srps srpr 0000 0000 0000 0000 11bh srcon1 srspe srscke reserved srsc1e srrpe srrcke reserved srrc1e 0000 0000 0000 0000 11ch ? unimplemented ? ? 11dh apfcon rxdtsel sdosel sssel --- t1gsel txcksel p1bsel ccp1sel 000- 0000 000- 0000 11eh ? unimplemented ? ? 11fh ? unimplemented ? ? bank 3 18ch ansela ? ? ? ansa4 ? ansa2 ansa1 ansa0 ---1 -111 ---1 -111 18dh to 190h ? unimplemented ? ? 191h eeadrl eeprom/program memory address register low byte 0000 0000 0000 0000 192h eeadrh ? (3) eeprom / program memory address register high byte 1000 0000 1000 0000 193h eedatl eeprom/program memory read data register low byte xxxx xxxx uuuu uuuu 194h eedath ? ? eeprom / program memory read data register high byte --xx xxxx --uu uuuu 195h eecon1 eepgd cfgs lwlo free wrerr wren wr rd 0000 x000 0000 q000 196h eecon2 eeprom control register 2 0000 0000 0000 0000 197h vregcon (2) ? ? ? ? ? ?vregpm reserved ---- --01 ---- --01 198h ? unimplemented ? ? 199h rcreg usart receive data register 0000 0000 0000 0000 19ah txreg usart transmit data register 0000 0000 0000 0000 19bh spbrgl baud rate generator data register low 0000 0000 0000 0000 19ch spbrgh baud rate generator data register high 0000 0000 0000 0000 19dh rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x 19eh txsta csrc tx9 txen sync sendb brgh trmt tx9d 0000 0010 0000 0010 19fh baudcon abdovf rcidl ? sckp brg16 ?wueabden 01-0 0-00 01-0 0-00 table 3-6: special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: these registers can be addressed from any bank. 2: pic12f1840 only. 3: unimplemented, read as ? 1 ?.
pic12(l)f1840 ds41441c-page 24 ? 2011-2012 microchip technology inc. bank 4 20ch wpua ? ? wpua5 wpua4 wpua3 wpua2 wpua1 wpua0 --11 1111 --11 1111 20dh to 210h ? unimplemented ? ? 211h ssp1buf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 212h ssp1add add<7:0> 0000 0000 0000 0000 213h ssp1msk msk<7:0> 1111 1111 1111 1111 214h ssp1stat smp cke d/a psr/w ua bf 0000 0000 0000 0000 215h ssp1con1 wcol ssp1ov ssp1en ckp ssp1m<3:0> 0000 0000 0000 0000 216h ssp1con2 gcen ackstat ackdt acken rcen pen rsen sen 0000 0000 0000 0000 217h ssp1con3 acktim pcie scie boen sdaht sbcde ahen dhen 0000 0000 0000 0000 218h to 21fh ? unimplemented ? ? bank 5 28ch to 290h ? unimplemented ? ? 291h ccpr1l capture/compare/pwm register 1 (lsb) xxxx xxxx uuuu uuuu 292h ccpr1h capture/compare/pwm register 1 (msb) xxxx xxxx uuuu uuuu 293h ccp1con p1m<1:0> dc1b<1:0> ccp1m<3:0> 0000 0000 0000 0000 294h pwm1con p1rsen p1dc<6:0> 0000 0000 0000 0000 295h ccp1as ccp1ase ccp1as<2:0> pss1ac<1:0> pss1bd<1:0> 0000 0000 0000 0000 296h pstr1con ? ? ? str1sync reserved reserved str1b str1a ---0 rr01 ---0 rr01 297h to 29fh ? unimplemented ? ? bank 6 30ch to 31fh ? unimplemented ? ? bank 7 38ch to 390h ? unimplemented ? ? 391h iocap ? ? iocap5 iocap4 iocap3 iocap2 iocap1 iocap0 --00 0000 --00 0000 392h iocan ? ? iocan5 iocan4 iocan3 iocan2 iocan1 iocan0 --00 0000 --00 0000 393h iocaf ? ? iocaf5 iocaf4 iocaf3 iocaf2 iocaf1 iocaf0 --00 0000 --00 0000 394h to 399h ? unimplemented ? ? 39ah clkrcon clkren clkroe clkrslr clkrdc<1:0> clkrdiv <2:0> 0011 0000 0011 0000 39bh ? unimplemented ? ? 39ch mdcon mden mdoe mdslr mdopol mdout ? ? mdbit 0010 ---0 0010 ---0 39dh mdsrc mdmsodis ? ? ? mdms<3:0> x--- xxxx u--- uuuu 39eh mdcarl mdclodis mdclpol mdclsync ? mdcl<3:0> xxx- xxxx uuu- uuuu 39fh mdcarh mdchodis m dchpol mdchsync ? mdch<3:0> xxx- xxxx uuu- uuuu table 3-6: special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: these registers can be addressed from any bank. 2: pic12f1840 only. 3: unimplemented, read as ? 1 ?.
? 2011-2012 microchip technology inc. ds41441c-page 25 pic12(l)f1840 banks 8-30 x0ch/ x8ch ? x1fh/ x9fh ? unimplemented ? ? bank 31 f8ch ? fe3h ? unimplemented ? ? fe4h status_ shad ? ? ? ? ? z_shad dc_shad c_shad ---- -xxx ---- -uuu fe5h wreg_ shad working register shadow 0000 0000 uuuu uuuu fe6h bsr_ shad ? ? ? bank select register shadow ---x xxxx ---u uuuu fe7h pclath_ shad ? program counter latch high register shadow -xxx xxxx uuuu uuuu fe8h fsr0l_ shad indirect data memory address 0 low pointer shadow xxxx xxxx uuuu uuuu fe9h fsr0h_ shad indirect data memory address 0 high pointer shadow xxxx xxxx uuuu uuuu feah fsr1l_ shad indirect data memory address 1 low pointer shadow xxxx xxxx uuuu uuuu febh fsr1h_ shad indirect data memory address 1 high pointer shadow xxxx xxxx uuuu uuuu fech ? unimplemented ? ? fedh stkptr ? ? ? current stack pointer ---1 1111 ---1 1111 feeh tosl top-of-stack low byte xxxx xxxx uuuu uuuu fefh tosh ? top-of-stack high byte -xxx xxxx -uuu uuuu table 3-6: special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: these registers can be addressed from any bank. 2: pic12f1840 only. 3: unimplemented, read as ? 1 ?.
pic12(l)f1840 ds41441c-page 26 ? 2011-2012 microchip technology inc. 3.4 pcl and pclath the program counter (pc) is 15 bits wide. the low byte comes from the pcl register, which is a readable and writable register. the high byte (pc<14:8>) is not directly readable or writable and comes from pclath. on any reset, the pc is cleared. figure 3-3 shows the five situations for the loading of the pc. figure 3-3: loading of pc in different situations 3.4.1 modifying pcl executing any instruction with the pcl register as the destination simultaneously causes the program coun- ter pc<14:8> bits (pch) to be replaced by the contents of the pclath register. this allows the entire contents of the program counter to be changed by writing the desired upper 7 bits to the pclath register. when the lower 8 bits are written to the pcl register, all 15 bits of the program counter will change to the values con- tained in the pclath register and those being written to the pcl register. 3.4.2 computed goto a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). when performing a table read using a computed goto method, care should be exercised if the table location crosses a pcl memory boundary (each 256-byte block). refer to application note an556, ?implementing a table read? (ds00556). 3.4.3 computed function calls a computed function call allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables. when performing a table read using a computed function call , care should be exercised if the table location crosses a pcl memory boundary (each 256-byte block). if using the call instruction, the pch<2:0> and pcl registers are loaded with the operand of the call instruction. pch<6:3> is loaded with pclath<6:3>. the callw instruction enables computed calls by com- bining pclath and w to form the destination address. a computed callw is accomplished by loading the w register with the desired address and executing callw . the pcl register is loaded with the value of w and pch is loaded with pclath. 3.4.4 branching the branching instructions add an offset to the pc. this allows relocatable code and code that crosses page boundaries. there are two forms of branching, brw and bra . the pc will have incremented to fetch the next instruction in both cases. when using either branching instruction, a pcl memory boundary may be crossed. if using brw , load the w register with the desired unsigned address and execute brw . the entire pc will be loaded with the address pc + 1 + w. if using bra , the entire pc will be loaded with pc + 1 +, the signed value of the operand of the bra instruction. pcl pch 0 14 pc 0 6 7 alu result 8 pclath pcl pch 0 14 pc 0 6 4 opcode <10:0> 11 pclath pcl pch 0 14 pc 0 6 7 w 8 pclath instruction with pcl as destination goto, call callw pcl pch 0 14 pc pc + w 15 brw pcl pch 0 14 pc pc + opcode <8:0> 15 bra
? 2011-2012 microchip technology inc. ds41441c-page 27 pic12(l)f1840 3.5 stack all devices have a 16-level x 15-bit wide hardware stack (refer to figures 3-4 through and 3-7 ). the stack space is not part of either program or data space. the pc is pushed onto the stack when call or callw instructions are executed or an interrupt causes a branch. the stack is poped in the event of a return , retlw or a retfie instruction execution. pclath is not affected by a push or pop operation. the stack operates as a circular buffer if the stvren bit is programmed to ? 0 ? (configuration words). this means that after the stack has been pushed sixteen times, the seventeenth push overwrites the value that was stored from the first push. the eighteenth push overwrites the second push (and so on). the stkovf and stkunf flag bits will be set on an over- flow/underflow, regardless of whether the reset is enabled. 3.5.1 accessing the stack the stack is available through the tosh, tosl and stkptr registers. stkptr is the current value of the stack pointer. tosh:tosl register pair points to the top of the stack. both registers are read/writable. tos is split into tosh and tosl due to the 15-bit size of the pc. to access the stack, adjust the value of stkptr, which will position tosh:tosl, then read/write to tosh:tosl. stkptr is 5 bits to allow detection of overflow and underflow. during normal program operation, call, callw and interrupts will increment stkptr while retlw , return , and retfie will decrement stkptr. at any time, stkptr can be inspected to see how much stack is left. the stkptr always points at the currently used place on the stack. therefore, a call or callw will increment the stkptr and then write the pc, and a return will unload the pc and then decrement the stkptr. reference figure 3-4 through figure 3-7 for examples of accessing the stack. figure 3-4: accessing the stack example 1 note 1: there are no instructions/mnemonics called push or pop. these are actions that occur from the execution of the call, callw , return , retlw and retfie instructions or the vectoring to an interrupt address. note: care should be taken when modifying the stkptr while interrupts are enabled. 0x0f 0x0e 0x0d 0x0c 0x0b 0x0a 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 0x0000 stkptr = 0x1f initial stack configuration: after reset, the stack is empty. the empty stack is initialized so the stack pointer is pointing at 0x1f. if the stack overflow/underflow reset is enabled, the tosh/tosl registers will return ? 0 ?. if the stack overflow/underflow reset is disabled, the tosh/tosl registers will return the contents of stack address 0x0f. 0x1f stkptr = 0x1f stack reset disabled (stvren = 0 ) stack reset enabled (stvren = 1 ) tosh:tosl tosh:tosl
pic12(l)f1840 ds41441c-page 28 ? 2011-2012 microchip technology inc. figure 3-5: accessing the stack example 2 figure 3-6: accessing the stack example 3 0x0f 0x0e 0x0d 0x0c 0x0b 0x0a 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 return address 0x00 stkptr = 0x00 this figure shows the stack configuration after the first call or a single interrupt. if a return instruction is executed, the return addre ss will be placed in the program counter and the stack pointer decremented to the empty state (0x1f). tosh:tosl 0x0f 0x0e 0x0d 0x0c 0x0b 0x0a 0x09 0x08 0x07 return address 0x06 return address 0x05 return address 0x04 return address 0x03 return address 0x02 return address 0x01 return address 0x00 stkptr = 0x06 after seven call s or six call s and an interrupt, the stack looks like the figure on the left. a series of return instructions will repeatedly place the return addresses into the program counter and pop the stack. tosh:tosl
? 2011-2012 microchip technology inc. ds41441c-page 29 pic12(l)f1840 figure 3-7: accessing the stack example 4 3.5.2 overflow/ underflow reset if the stvren bit in configuration words is programmed to ? 1 ?, the device will be reset if the stack is pushed beyond the sixteenth level or poped beyond the first level, setting the appropriate bits (stkovf or stkunf, respectively) in the pcon register. 3.6 indirect addressing the indfn registers are not physical registers. any instruction that accesses an indfn register actually accesses the register at the address specified by the file select registers (fsr). if the fsrn address specifies one of the two indfn registers, the read will return ? 0 ? and the write will not occur (though status bits may be affected). the fsrn register value is created by the pair fsrnh and fsrnl. the fsr registers form a 16- bit address that allows an addressing space with 65536 locations. these locations are divided into three memory regions: ? traditional data memory ? linear data memory ? program flash memory 0x0f 0x0e 0x0d 0x0c 0x0b 0x0a 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 return address 0x00 stkptr = 0x10 when the stack is full, the next call or an interrupt will set the stack pointer to 0x10. this is identical to address 0x00 so the stack will wrap and overwrite the return address at 0x00. if the stack overflow/underflow reset is enabled, a reset will occur and location 0x00 will not be overwritten. return address return address return address return address return address return address return address return address return address return address return address return address return address return address return address tosh:tosl
pic12(l)f1840 ds41441c-page 30 ? 2011-2012 microchip technology inc. figure 3-8: indirect addressing 0x0000 0x0fff traditional fsr address range data memory 0x1000 reserved linear data memory reserved 0x2000 0x29af 0x29b0 0x7fff 0x8000 0xffff 0x0000 0x0fff 0x0000 0x7fff program flash memory note: not all memory regions are completely implemented. consult device memory tables for memory limits. 0x1fff
? 2011-2012 microchip technology inc. ds41441c-page 31 pic12(l)f1840 3.6.1 traditional data memory the traditional data memory is a region from fsr address 0x000 to fsr address 0xfff. the addresses correspond to the absolute addresses of all sfr, gpr and common registers. figure 3-9: traditio nal data memory map indirect addressing direct addressing bank select location select 4bsr 6 0 from opcode fsrxl 70 bank select location select 00000 00001 00010 11111 0x00 0x7f bank 0 bank 1 bank 2 bank 31 0 fsrxh 70 0000
pic12(l)f1840 ds41441c-page 32 ? 2011-2012 microchip technology inc. 3.6.2 linear data memory the linear data memory is the region from fsr address 0x2000 to fsr address 0x29af. this region is a virtual region that points back to the 80-byte blocks of gpr memory in all the banks. unimplemented memory reads as 0x00. use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the fsr beyond one bank will go directly to the gpr memory of the next bank. the 16 bytes of common memory are not included in the linear data memory region. figure 3-10: linear data memory map 3.6.3 program flash memory to make constant data access easier, the entire program flash memory is mapped to the upper half of the fsr address space. when the msb of fsrnh is set, the lower 15 bits are the address in program memory which will be accessed through indf. only the lower 8 bits of each memory location is accessible via indf. writing to the program flash memory cannot be accomplished via the fsr/indf interface. all instructions that access program flash memory via the fsr/indf interface will require one additional instruction cycle to complete. figure 3-11: program flash memory map 7 0 1 7 0 0 location select 0x2000 fsrnh fsrnl 0x020 bank 0 0x06f 0x0a0 bank 1 0x0ef 0x120 bank 2 0x16f 0xf20 bank 30 0xf6f 0x29af 0 7 1 7 0 0 location select 0x8000 fsrnh fsrnl 0x0000 0x7fff 0xffff program flash memory (low 8 bits)
? 2011-2012 microchip technology inc. ds41441c-page 33 pic12(l)f1840 4.0 device configuration device configuration consists of configuration words, code protection and device id. 4.1 configuration words there are several configuration word bits that allow different oscillator and memory protection options. these are implemented as configuration word 1 at 8007h and configuration word 2 at 8008h. note: the debug bit in configuration word 2 is managed automatically by device development tools including debuggers and programmers. for normal device operation, this bit should be maintained as a ' 1 '.
pic12(l)f1840 ds41441c-page 34 ? 2011-2012 microchip technology inc. 4.2 register definitions: configuration words register 4-1: config1: configuration word 1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 fcmen ieso clkouten boren<1:0> cpd bit 13 bit 8 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 cp mclre pwrte wdte<1:0> fosc<2:0> bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?1? ?0? = bit is cleared ?1? = bit is set -n = value when blank or after bulk erase bit 13 fcmen: fail-safe clock monitor enable bit 1 = fail-safe clock monitor is enabled 0 = fail-safe clock monitor is disabled bit 12 ieso: internal external switchover bit 1 = internal/external switchover mode is enabled 0 = internal/external switchover mode is disabled bit 11 clkouten : clock out enable bit if fosc configuration bits are set to lp, xt, hs modes : this bit is ignored, clkout function is disabled. oscillator function on the clkout pin. all other fosc modes : 1 = clkout function is disabled. i/o function on the clkout pin. 0 = clkout function is enabled on the clkout pin bit 10-9 boren<1:0>: brown-out reset enable bits (1) 11 = bor enabled 10 = bor enabled during operation and disabled in sleep 01 = bor controlled by sboren bit of the borcon register 00 = bor disabled bit 8 cpd : data code protection bit (2) 1 = data memory code protection is disabled 0 = data memory code protection is enabled bit 7 cp : code protection bit (3) 1 = program memory code protection is disabled 0 = program memory code protection is enabled bit 6 mclre: mclr /v pp pin function select bit if lvp bit = 1 : this bit is ignored. if lvp bit = 0 : 1 =mclr /v pp pin function is mclr ; weak pull-up enabled. 0 =mclr /v pp pin function is digital input; mclr internally disabled; weak pull-up under control of wpue3 bit. bit 5 pwrte : power-up timer enable bit (1) 1 = pwrt disabled 0 = pwrt enabled note 1: enabling brown-out reset does not automatically enable power-up timer. 2: the entire data eeprom will be erased when the code protection is turned off during an erase. 3: the entire program memory will be erased when the code protection is turned off.
? 2011-2012 microchip technology inc. ds41441c-page 35 pic12(l)f1840 bit 4-3 wdte<1:0>: watchdog timer enable bit 11 = wdt enabled 10 = wdt enabled while running and disabled in sleep 01 = wdt controlled by the swdten bit in the wdtcon register 00 = wdt disabled bit 2-0 fosc<2:0>: oscillator selection bits 111 = ech: external clock, high-power mode (4-20 mhz): device clock supplied to clkin pin 110 = ecm: external clock, medium-power mode (0.5-4 mhz): device clock supplied to clkin pin 101 = ecl: external clock, low-power mode (0-0.5 mhz): device clock supplied to clkin pin 100 = intosc oscillator: i/o function on clkin pin 011 = extrc oscillator: external rc circuit connected to clkin pin 010 = hs oscillator: high-speed crystal/resonator connected between osc1 and osc2 pins 001 = xt oscillator: crystal/resonator connected between osc1 and osc2 pins 000 = lp oscillator: low-power crystal connected between osc1 and osc2 pins register 4-1: conf ig1: config uration word 1 (continued) note 1: enabling brown-out reset does not automatically enable power-up timer. 2: the entire data eeprom will be erased when the code protection is turned off during an erase. 3: the entire program memory will be erased when the code protection is turned off.
pic12(l)f1840 ds41441c-page 36 ? 2011-2012 microchip technology inc. register 4-2: config2: configuration word 2 r/p-1 r/p-1 u-1 r/p-1 r/p-1 r/p-1 lvp (1) debug (2) ?borvstvrenpllen bit 13 bit 8 u-1 u-1 r-1 u-1 u-1 u-1 r/p-1 r/p-1 ? ? reserved ? ? ?wrt<1:0> bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?1? ?0? = bit is cleared ?1? = bit is set -n = value when blank or after bulk erase bit 13 lvp: low-voltage programming enable bit (1) 1 = low-voltage programming enabled 0 = high-voltage on mclr must be used for programming bit 12 debug : in-circuit debugger mode bit (2) 1 = in-circuit debugger disabled, icspclk and icspdat are general purpose i/o pins 0 = in-circuit debugger enabled, icspclk and icspdat are dedicated to the debugger bit 11 unimplemented: read as ? 1 ? bit 10 borv: brown-out reset voltage selection bit (3) 1 = brown-out reset voltage ( vbor ), low trip point selected. 0 = brown-out reset voltage ( vbor ), high trip point selected. bit 9 stvren: stack overflow/underflow reset enable bit 1 = stack overflow or underflow will cause a reset 0 = stack overflow or underflow will not cause a reset bit 8 pllen: pll enable bit 1 = 4xpll enabled 0 = 4xpll disabled bit 7-5 unimplemented: read as ? 1 ? bit 4 reserved : this location should be programmed to a ? 1 ?. bit 3-2 unimplemented: read as ? 1 ? bit 1-0 wrt<1:0>: flash memory self-write protection bits 11 = write protection off 10 = 000h to 1ffh write-protected, 200h to fffh may be modified 01 = 000h to 7ffh write-protected, 800h to fffh may be modified 00 = 000h to fffh write-protected, no addresses may be modified note 1: the lvp bit cannot be programmed to ? 0 ? when programming mode is entered via lvp. 2: the debug bit in configuration words is managed automatically by device development tools including debuggers and programmers. for normal device operation, this bit should be maintained as a ' 1 '. 3: see vbor parameter for specific trip point voltages.
? 2011-2012 microchip technology inc. ds41441c-page 37 pic12(l)f1840 4.3 code protection code protection allows the device to be protected from unauthorized access. program memory protection and data eeprom protection are controlled independently. internal access to the program memory and data eeprom are unaffected by any code protection setting. 4.3.1 program memory protection the entire program memory space is protected from external reads and writes by the cp bit in configuration words. when cp = 0 , external reads and writes of program memory are inhibited and a read will return all ? 0 ?s. the cpu can continue to read program memory, regardless of the protection bit settings. writing the program memory is dependent upon the write protection setting. see section 4.4 ?write protection? for more information. 4.3.2 data eeprom protection the entire data eeprom is protected from external reads and writes by the cpd bit. when cpd = 0 , external reads and writes of data eeprom are inhibited. the cpu can continue to read and write data eeprom regardless of the protection bit settings. 4.4 write protection write protection allows the device to be protected from unintended self-writes. applications, such as bootloader software, can be protected while allowing other regions of the program memory to be modified. the wrt<1:0> bits in configuration words define the size of the program memory block that is protected. 4.5 user id four memory locations (8000h-8003h) are designated as id locations where the user can store checksum or other code identification numbers. these locations are readable and writable during normal execution. see section 11.5 ?user id, device id and configuration word access? for more information on accessing these memory locations. for more information on checksum calculation, see the ? pic16f/lf1847/pic12f/lf1840 memory programming specification ? (ds41439).
pic12(l)f1840 ds41441c-page 38 ? 2011-2012 microchip technology inc. 4.6 device id and revision id the memory location 8006h is where the device id and revision id are stored. the upper nine bits hold the device id. the lower five bits hold the revision id. see section 11.5 ?user id, device id and configuration word access? for more information on accessing these memory locations. development tools, such as device programmers and debuggers, may be used to read the device id and revision id. register 4-3: devid: device id register rrrrrr dev<8:3> bit 13 bit 8 rrrrrrrr dev<2:0> rev<4:0> bit 7 bit 0 legend: r = readable bit ?1? = bit is set ?0? = bit is cleared bit 13-5 dev<8:0>: device id bits bit 4-0 rev<4:0>: revision id bits these bits are used to identify the revision (see table under dev<8:0> above). device devid<13:0> values dev<8:0> rev<4:0> pic12f1840 011 011 100 x xxxx pic12lf1840 011 011 110 x xxxx
? 2011-2012 microchip technology inc. ds41441c-page 39 pic12(l)f1840 5.0 oscillator module (with fail-safe clock monitor) 5.1 overview the oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing perfor- mance and minimizing power consumption. figure 5-1 illustrates a block diagram of the oscillator module. clock sources can be supplied from external oscillators, quartz crystal resonators, ceramic resonators and resistor-capacitor (rc) circuits. in addition, the system clock source can be supplied from one of two internal oscillators and pll circuits, with a choice of speeds selectable via software. additional clock features include: ? selectable system clock source between external or internal sources via software. ? two-speed start-up mode, which minimizes latency between external oscillator start-up and code execution. ? fail-safe clock monitor (fscm) designed to detect a failure of the external clock source (lp, xt, hs, ec or rc modes) and switch automatically to the internal oscillator. ? oscillator start-up timer (ost) ensures stability of crystal oscillator sources. the oscillator module can be configured in one of eight clock modes. 1. ecl ? external clock low-power mode (0 mhz to 0.5 mhz) 2. ecm ? external clock medium-power mode (0.5 mhz to 4 mhz) 3. ech ? external clock high-power mode (4 mhz to 32 mhz) 4. lp ? 32 khz low-power crystal mode. 5. xt ? medium gain crystal or ceramic resonator oscillator mode (up to 4 mhz) 6. hs ? high gain crystal or ceramic resonator mode (4 mhz to 20 mhz) 7. rc ? external resistor-capacitor (rc). 8. intosc ? internal oscillator (31 khz to 32 mhz). clock source modes are selected by the fosc<2:0> bits in the configuration words. the fosc bits determine the type of oscillator that will be used when the device is first powered. the ec clock mode relies on an external logic level signal as the device clock source. the lp, xt, and hs clock modes require an external crystal or resonator to be connected to the device. each mode is optimized for a different frequency range. the rc clock mode requires an external resistor and capacitor to set the oscillator frequency. the intosc internal oscillator block produces low, medium, and high-frequency clock sources, designated lfintosc, mfintosc and hfintosc. (see internal oscillator block, figure 5-1 ). a wide selection of device clock frequencies may be derived from these three clock sources.
pic12(l)f1840 ds41441c-page 40 ? 2011-2012 microchip technology inc. figure 5-1: simplified pic ? mcu clock source block diagram 4 x pll fosc<2:0> oscillator t1oscen enable oscillator t1oso t1osi clock source option for other modules osc1 osc2 sleep lp, xt, hs, rc, ec t1osc cpu and postscaler mux mux 16 mhz 8 mhz 4 mhz 2 mhz 1 mhz 250 khz 500 khz ircf<3:0> 31 khz 500 khz source internal oscillator block wdt, pwrt, fail-safe clock monitor 16 mhz internal oscillator (hfintosc) clock control scs<1:0> hfpll 31 khz (lfintosc) two-speed start-up and other modules oscillator 31 khz source 500 khz (mfintosc) 125 khz 31.25 khz 62.5 khz fosc<2:0> = 100 peripherals sleep external timer1
? 2011-2012 microchip technology inc. ds41441c-page 41 pic12(l)f1840 5.2 clock source types clock sources can be classified as external or internal. external clock sources rely on external circuitry for the clock source to function. examples are: oscillator mod- ules (ec mode), quartz crystal resonators or ceramic resonators (lp, xt and hs modes) and resis- tor-capacitor (rc) mode circuits. internal clock sources are contained within the oscilla- tor module. the internal oscillator block has two inter- nal oscillators and a dedicated phase-lock loop (hfpll) that are used to generate three internal sys- tem clock sources: the 16 mhz high-frequency inter- nal oscillator (hfintosc), 500 khz (mfintosc) and the 31 khz low-frequency internal oscillator (lfin- tosc). the system clock can be selected between external or internal clock sources via the system clock select (scs) bits in the osccon register. see section 5.3 ?clock switching? for additional information. 5.2.1 external clock sources an external clock source can be used as the device system clock by performing one of the following actions: ? program the fosc<2:0> bits in the configuration words to select an external clock source that will be used as the default system clock upon a device reset. ? write the scs<1:0> bits in the osccon register to switch the system clock source to: - timer1 oscillator during run-time, or - an external clock source determined by the value of the fosc bits. see section 5.3 ?clock switching? for more informa- tion. 5.2.1.1 ec mode the external clock (ec) mode allows an externally generated logic level signal to be the system clock source. when operating in this mode, an external clock source is connected to the osc1 input. osc2/clkout is available for general purpose i/o or clkout. figure 5-2 shows the pin connections for ec mode. ec mode has three power modes to select from through configuration words: ? high power, 4-32 mhz (fosc = 111 ) ? medium power, 0.5-4 mhz (fosc = 110 ) ? low power, 0-0.5 mhz (fosc = 101 ) the oscillator start-up timer (ost) is disabled when ec mode is selected. therefore, there is no delay in operation after a power-on reset (por) or wake-up from sleep. because the pic ? mcu design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. upon restarting the external clock, the device will resume operation as if no time had elapsed. figure 5-2: external clock (ec) mode operation 5.2.1.2 lp, xt, hs modes the lp, xt and hs modes support the use of quartz crystal resonators or ceramic resonators connected to osc1 and osc2 ( figure 5-3 ). the three modes select a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed. lp oscillator mode selects the lowest gain setting of the internal inverter-amplifier. lp mode current consumption is the least of the three modes. this mode is designed to drive only 32.768 khz tuning-fork type crystals (watch crystals). xt oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. xt mode current consumption is the medium of the three modes. this mode is best suited to drive resonators with a medium drive level specification. hs oscillator mode selects the highest gain setting of the internal inverter-amplifier. hs mode current consumption is the highest of the three modes. this mode is best suited for resonators that require a high drive setting. figure 5-3 and figure 5-4 show typical circuits for quartz crystal and ceramic resonators, respectively. osc1/clkin osc2/clkout clock from ext. system pic ? mcu f osc /4 or i/o (1) note 1: output depends upon clkouten bit of the configuration words.
pic12(l)f1840 ds41441c-page 42 ? 2011-2012 microchip technology inc. figure 5-3: quartz crystal operation (lp, xt or hs mode) figure 5-4: ceramic resonator operation (xt or hs mode) 5.2.1.3 oscillator start-up timer (ost) if the oscillator module is configured for lp, xt or hs modes, the oscillator start-up timer (ost) counts 1024 oscillations from osc1. this occurs following a power-on reset (por) and when the power-up timer (pwrt) has expired (if configured), or a wake-up from sleep. during this time, the program counter does not increment and program execution is suspended, unless either fscm or two-speed start-up are enabled. in this case, code will continue to execute at the selected intosc frequency while the ost is counting. the ost ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the oscillator module. in order to minimize latency between external oscillator start-up and code execution, the two-speed clock start-up mode can be selected (see section 5.4 ?two-speed clock start-up mode? ). note 1: quartz crystal characteristics vary according to type, package and manufacturer. the user should consult the manufacturer data sheets for specifications and recommended application. 2: always verify oscillator performance over the v dd and temperature range that is expected for the application. 3: for oscillator design assistance, reference the following microchip applications notes: ? an826, ? crystal oscillator basics and crystal selection for rfpic ? and pic ? devices ? (ds00826) ? an849, ? basic pic ? oscillator design ? (ds00849) ? an943, ? practical pic ? oscillator analysis and design ? (ds00943) ? an949, ? making your oscillator work ? (ds00949) note 1: a series resistor (r s ) may be required for quartz crystals with low drive level. 2: the value of r f varies with the oscillator mode selected (typically between 2 m ? to 10 m ?? . c1 c2 quartz r s (1) osc1/clkin r f (2) sleep to internal logic pic ? mcu crystal osc2/clkout note 1: a series resistor (r s ) may be required for ceramic resonators with low drive level. 2: the value of r f varies with the oscillator mode selected (typically between 2 m ? to 10 m ?? . 3: an additional parallel feedback resistor (r p ) may be required for proper ceramic resonator operation. c1 c2 ceramic r s (1) osc1/clkin r f (2) sleep to internal logic pic ? mcu r p (3) resonator osc2/clkout
? 2011-2012 microchip technology inc. ds41441c-page 43 pic12(l)f1840 5.2.1.4 4x pll the oscillator module contains a 4x pll that can be used with both external and internal clock sources to provide a system clock source. the input frequency for the 4x pll must fall within specifications. see the pll clock timing specifications in section 30.0 ?electrical specifications? . the 4x pll may be enabled for use by one of two methods: 1. program the pllen bit in configuration words to a ? 1 ?. 2. write the spllen bit in the osccon register to a ? 1 ?. if the pllen bit in configuration words is programmed to a ? 1 ?, then the value of spllen is ignored. 5.2.1.5 timer1 oscillator the timer1 oscillator is a separate crystal oscillator that is associated with the timer1 peripheral. it is opti- mized for timekeeping operations with a 32.768 khz crystal connected between the t1oso and t1osi device pins. the timer1 oscillator can be used as an alternate system clock source and can be selected during run-time using clock switching. refer to section 5.3 ?clock switching? for more information. figure 5-5: quartz crystal operation (timer1 oscillator) 5.2.1.6 external rc mode the external resistor-capacitor (rc) modes support the use of an external rc circuit. this allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. the rc circuit connects to osc1. osc2/clkout is available for general purpose i/o or clkout. the function of the osc2/clkout pin is determined by the c lkouten bit in configuration words. figure 5-6 shows the external rc mode connections. c1 c2 32.768 khz t1osi to internal logic pic ? mcu crystal t1oso quartz note 1: quartz crystal characteristics vary according to type, package and manufacturer. the user should consult the manufacturer data sheets for specifications and recommended application. 2: always verify oscillator performance over the v dd and temperature range that is expected for the application. 3: for oscillator design assistance, reference the following microchip applications notes: ? an826, ? crystal oscillator basics and crystal selection for rfpic ? and pic ? devices ? (ds00826) ? an849, ? basic pic ? oscillator design ? (ds00849) ? an943, ? practical pic ? oscillator analysis and design ? (ds00943) ? an949, ? making your oscillator work ? (ds00949) ? tb097, ? interfacing a micro crystal ms1v-t1k 32.768 khz tuning fork crystal to a pic16f690/ss ? (ds91097) ? an1288, ? design practices for low-power external oscillators ? (ds01288)
pic12(l)f1840 ds41441c-page 44 ? 2011-2012 microchip technology inc. figure 5-6: external rc modes the rc oscillator frequency is a function of the supply voltage, the resistor (r ext ) and capacitor (c ext ) values and the operating temperature. other factors affecting the oscillator frequency are: ? threshold voltage variation ? component tolerances ? packaging variations in capacitance the user also needs to take into account variation due to tolerance of external rc components used. 5.2.2 internal clock sources the device may be configured to use the internal oscil- lator block as the system clock by performing one of the following actions: ? program the fosc<2:0> bits in configuration words to select the intosc clock source, which will be used as the default system clock upon a device reset. ? write the scs<1:0> bits in the osccon register to switch the system clock source to the internal oscillator during run-time. see section 5.3 ?clock switching? for more information. in intosc mode, osc1/clkin is available for general purpose i/o. osc2/clkout is available for general purpose i/o or clkout. the function of the osc2/clkout pin is determined by the c lkouten bit in configuration words. the internal oscillator block has two independent oscillators and a dedicated phase-lock loop, hfpll that can produce one of three internal system clock sources. 1. the hfintosc (high-frequency internal oscillator) is factory calibrated and operates at 16 mhz. the hfintosc source is generated from the 500 khz mfintosc source and the dedicated phase-lock loop, hfpll. the frequency of the hfintosc can be user-adjusted via software using the osctune register ( register 5-3 ). 2. the mfintosc (medium-frequency internal oscillator) is factory calibrated and operates at 500 khz. the frequency of the mfintosc can be user-adjusted via software using the osctune register ( register 5-3 ). 3. the lfintosc (low-frequency internal oscillator) is uncalibrated and operates at 31 khz. osc2/clkout c ext r ext pic ? mcu osc1/clkin f osc /4 or internal clock v dd v ss recommended values: 10 k ? ? r ext ? 100 k ? , <3v 3 k ? ? r ext ? 100 k ? , 3-5v c ext > 20 pf, 2-5v note 1: output depends upon clkouten bit of the configuration words. i/o (1)
? 2011-2012 microchip technology inc. ds41441c-page 45 pic12(l)f1840 5.2.2.1 hfintosc the high-frequency internal oscillator (hfintosc) is a factory calibrated 16 mhz internal clock source. the frequency of the hfintosc can be altered via software using the osctune register ( register 5-3 ). the output of the hfintosc connects to a postscaler and multiplexer (see figure 5-1 ). one of multiple frequencies derived from the hfintosc can be selected via software using the ircf<3:0> bits of the osccon register. see section 5.2.2.7 ?internal oscillator clock switch timing? for more information. the hfintosc is enabled by: ? configure the ircf<3:0> bits of the osccon register for the desired hf frequency, and ?fosc<2:0> = 100 , or ? set the system clock source (scs) bits of the osccon register to ? 1x ?. a fast start-up oscillator allows internal circuits to power up and stabilize before switching to hfintosc. the high-frequency internal oscillator ready bit (hfiofr) of the oscstat register indicates when the hfintosc is running. the high-frequency internal oscillator status locked bit (hfiofl) of the oscstat register indicates when the hfintosc is running within 2% of its final value. the high-frequency internal oscillator stable bit (hfiofs) of the oscstat register indicates when the hfintosc is running within 0.5% of its final value. 5.2.2.2 mfintosc the medium-frequency internal oscillator (mfintosc) is a factory calibrated 500 khz internal clock source. the frequency of the mfintosc can be altered via software using the osctune register ( register 5-3 ). the output of the mfintosc connects to a postscaler and multiplexer (see figure 5-1 ). one of nine frequencies derived from the mfintosc can be selected via software using the ircf<3:0> bits of the osccon register. see section 5.2.2.7 ?internal oscillator clock switch timing? for more information. the mfintosc is enabled by: ? configure the ircf<3:0> bits of the osccon register for the desired hf frequency, and ?fosc<2:0> = 100 , or ? set the system clock source (scs) bits of the osccon register to ? 1x ? the medium frequency internal oscillator ready bit (mfiofr) of the oscstat register indicates when the mfintosc is running. 5.2.2.3 internal oscillator frequency adjustment the 500 khz internal oscillator is factory calibrated. this internal oscillator can be adjusted in software by writing to the osctune register ( register 5-3 ). since the hfintosc and mfintosc clock sources are derived from the 500 khz internal oscillator a change in the osctune register value will apply to both. the default value of the osctune register is ? 0 ?. the value is a 6-bit two?s complement number. a value of 1fh will provide an adjustment to the maximum frequency. a value of 20h will provide an adjustment to the minimum frequency. when the osctune register is modified, the oscillator frequency will begin shifting to the new frequency. code execution continues during this shift. there is no indication that the shift has occurred. osctune does not affect the lfintosc frequency. operation of features that depend on the lfintosc clock source frequency, such as the power-up timer (pwrt), watchdog timer (wdt), fail-safe clock monitor (fscm) and peripherals, are not affected by the change in frequency. 5.2.2.4 lfintosc the low-frequency internal oscillator (lfintosc) is an uncalibrated 31 khz internal clock source. the output of the lfintosc connects to a multiplexer (see figure 5-1 ). select 31 khz, via software, using the ircf<3:0> bits of the osccon register. see section 5.2.2.7 ?internal oscillator clock switch timing? for more information. the lfintosc is also the frequency for the power-up timer (pwrt), watchdog timer (wdt) and fail-safe clock monitor (fscm). the lfintosc is enabled by selecting 31 khz (ircf<3:0> bits of the osccon register = 000) as the system clock source (scs bits of the osccon register = 1x ), or when any of the following are enabled: ? configure the ircf<3:0> bits of the osccon register for the desired lf frequency, and ?fosc<2:0> = 100 , or ? set the system clock source (scs) bits of the osccon register to ? 1x ? peripherals that use the lfintosc are: ? power-up timer (pwrt) ? watchdog timer (wdt) ? fail-safe clock monitor (fscm) the low-frequency internal oscillator ready bit (lfiofr) of the oscstat register indicates when the lfintosc is running.
pic12(l)f1840 ds41441c-page 46 ? 2011-2012 microchip technology inc. 5.2.2.5 internal oscillator frequency selection the system clock speed can be selected via software using the internal oscillator frequency select bits ircf<3:0> of the osccon register. the output of the 16 mhz hfintosc postscaler and lfintosc connects to a multiplexer (see figure 5-1 ). the internal oscillator frequency select bits ircf<3:0> of the osccon register select the frequency output of the internal oscillators. one of the following frequencies can be selected via software: ? 32 mhz (requires 4x pll) ?16 mhz ?8 mhz ?4 mhz ?2 mhz ?1 mhz ? 500 khz (default after reset) ? 250 khz ? 125 khz ? 62.5 khz ? 31.25 khz ? 31 khz (lfintosc) the ircf<3:0> bits of the osccon register allow duplicate selections for some frequencies. these dupli- cate choices can offer system design trade-offs. lower power consumption can be obtained when changing oscillator sources for a given frequency. faster transi- tion times can be obtained between frequency changes that use the same oscillator source. 5.2.2.6 32 mhz internal oscillator frequency selection the internal oscillator block can be used with the 4x pll associated with the external oscillator block to produce a 32 mhz internal system clock source. the following settings are required to use the 32 mhz inter- nal clock source: ? the fosc bits in configuration words must be set to use the intosc source as the device sys- tem clock (fosc<2:0> = 100 ). ? the scs bits in the osccon register must be cleared to use the clock determined by fosc<2:0> in configuration words (scs<1:0> = 00 ). ? the ircf bits in the osccon register must be set to the 8 mhz hfintosc set to use (ircf<3:0> = 1110 ). ? the spllen bit in the osccon register must be set to enable the 4xpll, or the pllen bit of the configuration words must be programmed to a ? 1 ?. the 4x pll is not available for use with the internal oscillator when the scs bits of the osccon register are set to ? 1x ?. the scs bits must be set to ? 00 ? to use the 4x pll with the internal oscillator. note: following any reset, the ircf<3:0> bits of the osccon register are set to ? 0111 ? and the frequency selection is set to 500 khz. the user can modify the ircf bits to select a different frequency. note: when using the pllen bit of the configuration words , the 4x pll cannot be disabled by software and the 8 mhz hfintosc option will no longer be available.
? 2011-2012 microchip technology inc. ds41441c-page 47 pic12(l)f1840 5.2.2.7 internal oscillator clock switch timing when switching between the hfintosc, mfintosc and the lfintosc, the new oscillator may already be shut down to save power (see figure 5-7 ). if this is the case, there is a delay after the ircf<3:0> bits of the osccon register are modified before the frequency selection takes place. the oscstat register will reflect the current active status of the hfintosc, mfintosc and lfintosc oscillators. the sequence of a frequency selection is as follows: 1. ircf<3:0> bits of the osccon register are modified. 2. if the new clock is shut down, a clock start-up delay is started. 3. clock switch circuitry waits for a falling edge of the current clock. 4. the current clock is held low and the clock switch circuitry waits for a rising edge in the new clock. 5. the new clock is now active. 6. the oscstat register is updated as required. 7. clock switch is complete. see figure 5-7 for more details. if the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay before the new frequency is selected. clock switching time delays are shown in table 5-1 . start-up delay specifications are located in the oscillator tables of section 30.0 ?electrical specifications?
pic12(l)f1840 ds41441c-page 48 ? 2011-2012 microchip technology inc. figure 5-7: internal oscillator switch timing hfintosc/ lfintosc ircf <3:0> system clock hfintosc/ lfintosc ircf <3:0> system clock ?? 0 ?? 0 ?? 0 ?? 0 start-up time 2-cycle sync running 2-cycle sync running hfintosc/ lfintosc (fscm and wdt disabled) hfintosc/ lfintosc (either fscm or wdt enabled) lfintosc hfintosc/ ircf <3:0> system clock = 0 ? 0 start-up time 2-cycle sync running lfintosc hfintosc/mfintosc lfintosc turns off unless wdt or fscm is enabled mfintosc mfintosc mfintosc mfintosc mfintosc
? 2011-2012 microchip technology inc. ds41441c-page 49 pic12(l)f1840 5.3 clock switching the system clock source can be switched between external and internal clock sources via software using the system clock select (scs) bits of the osccon register. the following clock sources can be selected using the scs bits: ? default system oscillator determined by fosc bits in configuration words ? timer1 32 khz crystal oscillator ? internal oscillator block (intosc) 5.3.1 system clock select (scs) bits the system clock select (scs) bits of the osccon register selects the system clock source that is used for the cpu and peripherals. ? when the scs bits of the osccon register = 00 , the system clock source is determined by value of the fosc<2:0> bits in the configuration words. ? when the scs bits of the osccon register = 01 , the system clock source is the timer1 oscillator. ? when the scs bits of the osccon register = 1x , the system clock source is chosen by the internal oscillator frequency selected by the ircf<3:0> bits of the osccon register. after a reset, the scs bits of the osccon register are always cleared. when switching between clock sources, a delay is required to allow the new clock to stabilize. these oscil- lator delays are shown in table 5-1 . 5.3.2 oscillator start-up timer status (osts) bit the oscillator start-up timer status (osts) bit of the oscstat register indicates whether the system clock is running from the external clock source, as defined by the fosc<2:0> bits in the configuration words, or from the internal clock source. in particular, osts indicates that the oscillator start-up timer (ost) has timed out for lp, xt or hs modes. the ost does not reflect the status of the timer1 oscillator. 5.3.3 timer1 oscillator the timer1 oscillator is a separate crystal oscillator associated with the timer1 peripheral. it is optimized for timekeeping operations with a 32.768 khz crystal connected between the t1oso and t1osi device pins. the timer1 oscillator is enabled using the t1oscen control bit in the t1con register. see section 21.0 ?timer1 module with gate control? for more information about the timer1 peripheral. 5.3.4 timer1 oscillator ready (t1oscr) bit the user must ensure that the timer1 oscillator is ready to be used before it is selected as a system clock source. the timer1 oscillator ready (t1oscr) bit of the oscstat register indicates whether the timer1 oscillator is ready to be used. after the t1oscr bit is set, the scs bits can be configured to select the timer1 oscillator. note: any automatic clock switch, which may occur from two-speed start-up or fail-safe clock monitor, does not update the scs bits of the osccon register. the user can monitor the osts bit of the oscstat register to determine the current system clock source.
pic12(l)f1840 ds41441c-page 50 ? 2011-2012 microchip technology inc. 5.4 two-speed clock start-up mode two-speed start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. in applications that make heavy use of the sleep mode, two-speed start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device. this mode allows the application to wake-up from sleep, perform a few instructions using the intosc internal oscillator block as the clock source and go back to sleep without waiting for the external oscillator to become stable. two-speed start-up provides benefits when the oscil- lator module is configured for lp, xt or hs modes. the oscillator start-up timer (ost) is enabled for these modes and must count 1024 oscillations before the oscillator can be used as the system clock source. if the oscillator module is configured for any mode other than lp, xt or hs mode, then two-speed start-up is disabled. this is because the external clock oscillator does not require any stabilization time after por or an exit from sleep. if the ost count reaches 1024 before the device enters sleep mode, the osts bit of the oscstat register is set and program execution switches to the external oscillator. however, the system may never operate from the external oscillator if the time spent awake is very short. 5.4.1 two-speed start-up mode configuration two-speed start-up mode is configured by the following settings: ? ieso (of the configuration words) = 1 ; inter- nal/external switchover bit (two-speed start-up mode enabled). ? scs (of the osccon register) = 00 . ? fosc<2:0> bits in the configuration words configured for lp, xt or hs mode. two-speed start-up mode is entered after: ? power-on reset (por) and, if enabled, after power-up timer (pwrt) has expired, or ? wake-up from sleep. table 5-1: oscillator switching delays note: executing a sleep instruction will abort the oscillator start-up time and will cause the osts bit of the oscstat register to remain clear. switch from switch to frequency oscillator delay sleep/por lfintosc (1) mfintosc (1) hfintosc (1) 31 khz 31.25 khz-500 khz 31.25khz-16mhz oscillator warm-up delay (t warm ) sleep/por ec, rc (1) dc ? 32 mhz 2 cycles lfintosc ec, rc (1) dc ? 32 mhz 1 cycle of each sleep/por timer1 oscillator lp, xt, hs (1) 32 khz-20 mhz 1024 clock cycles (ost) any clock source mfintosc (1) hfintosc (1) 31.25 khz-500 khz 31.25khz-16mhz 2 ? s (approx.) any clock source lfintosc (1) 31 khz 1 cycle of each any clock source timer1 oscillator 32 khz 1024 clock cycles (ost) pll inactive pll active 16-32 mhz 2 ms (approx.) note 1: pll inactive.
? 2011-2012 microchip technology inc. ds41441c-page 51 pic12(l)f1840 5.4.2 two-speed start-up sequence 1. wake-up from power-on reset or sleep. 2. instructions begin execution by the internal oscillator at the frequency set in the ircf<3:0> bits of the osccon register. 3. ost enabled to count 1024 clock cycles. 4. ost timed out, wait for falling edge of the internal oscillator. 5. osts is set. 6. system clock held low until the next falling edge of new clock (lp, xt or hs mode). 7. system clock is switched to external clock source. 5.4.3 checking two-speed clock status checking the state of the osts bit of the oscstat register will confirm if the microcontroller is running from the external clock source, as defined by the fosc<2:0> bits in the configuration words, or the internal oscillator. figure 5-8: two-speed start-up 0 1 1022 1023 pc + 1 t ost t intosc osc1 osc2 program counter system clock pc - n pc
pic12(l)f1840 ds41441c-page 52 ? 2011-2012 microchip technology inc. 5.5 fail-safe clock monitor the fail-safe clock monitor (fscm) allows the device to continue operating should the external oscillator fail. the fscm can detect oscillator failure any time after the oscillator start-up timer (ost) has expired. the fscm is enabled by setting the fcmen bit in the configuration words. the fscm is applicable to all external oscillator modes (lp, xt, hs, ec, timer1 oscillator and rc). figure 5-9: fscm block diagram 5.5.1 fail-safe detection the fscm module detects a failed oscillator by comparing the external oscillator to the fscm sample clock. the sample clock is generated by dividing the lfintosc by 64. see figure 5-9 . inside the fail detector block is a latch. the external clock sets the latch on each falling edge of the external clock. the sample clock clears the latch on each rising edge of the sample clock. a failure is detected when an entire half-cycle of the sample clock elapses before the external clock goes low. 5.5.2 fail-safe operation when the external clock fails, the fscm switches the device clock to an internal clock source and sets the bit flag osfif of the pir2 register. setting this flag will generate an interrupt if the osfie bit of the pie2 register is also set. the device firmware can then take steps to mitigate the problems that may arise from a failed clock. the system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation. the internal clock source chosen by the fscm is determined by the ircf<3:0> bits of the osccon register. this allows the internal oscillator to be configured before a failure occurs. 5.5.3 fail-safe condition clearing the fail-safe condition is cleared after a reset, executing a sleep instruction or changing the scs bits of the osccon register. when the scs bits are changed, the ost is restarted. while the ost is running, the device continues to operate from the intosc selected in osccon. when the ost times out, the fail-safe condition is cleared after successfully switching to the external clock source. the osfif bit should be cleared prior to switching to the external clock source. if the fail-safe condition still exists, the osfif flag will again become set by hardware. 5.5.4 reset or wake-up from sleep the fscm is designed to detect an oscillator failure after the oscillator start-up timer (ost) has expired. the ost is used after waking up from sleep and after any type of reset. the ost is not used with the ec or rc clock modes so that the fscm will be active as soon as the reset or wake-up has completed. when the fscm is enabled, the two-speed start-up is also enabled. therefore, the device will always be executing code while the ost is operating. external lfintosc 64 s r q 31 khz (~32 ? s) 488 hz (~2 ms) clock monitor latch clock failure detected oscillator clock q sample clock note: due to the wide range of oscillator start-up times, the fail-safe circuit is not active during oscillator start-up (i.e., after exiting reset or sleep). after an appropriate amount of time, the user should check the status bits in the oscstat register to verify the oscillator start-up and that the system clock switchover has successfully completed.
? 2011-2012 microchip technology inc. ds41441c-page 53 pic12(l)f1840 figure 5-10: fscm timing diagram oscfif system clock output sample clock failure detected oscillator failure note: the system clock is normally at a much higher frequency than the sample clock. the relative frequencies in this example have been chosen for clarity. (q) te s t test test clock monitor output
pic12(l)f1840 ds41441c-page 54 ? 2011-2012 microchip technology inc. 5.6 register definitions: oscillator control register 5-1: osccon: os cillator control register r/w-0/0 r/w-0/0 r/w-1/1 r/w-1/1 r/w-1/1 u-0 r/w-0/0 r/w-0/0 spllen ircf<3:0> ? scs<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 spllen: software pll enable bit if pllen in configuration words = 1 : spllen bit is ignored. 4x pll is always enabled (subject to oscillator requirements) if pllen in configuration words = 0 : 1 = 4x pll is enabled 0 = 4x pll is disabled bit 6-3 ircf<3:0>: internal oscillator frequency select bits 1111 = 16 mhz hf 1110 = 8 mhz or 32 mhz hf(see section 5.2.2.1 ?hfintosc? ) 1101 =4mhz hf 1100 =2mhz hf 1011 =1mhz hf 1010 = 500 khz hf (1) 1001 = 250 khz hf (1) 1000 = 125 khz hf (1) 0111 = 500 khz mf (default upon reset) 0110 = 250 khz mf 0101 = 125 khz mf 0100 = 62.5 khz mf 0011 = 31.25 khz hf (1) 0010 = 31.25 khz mf 000x =31khz lf bit 2 unimplemented: read as ? 0 ? bit 1-0 scs<1:0>: system clock select bits 1x = internal oscillator block 01 = timer1 oscillator 00 = clock determined by fosc<2:0> in configuration words. note 1: duplicate frequency derived from hfintosc.
? 2011-2012 microchip technology inc. ds41441c-page 55 pic12(l)f1840 register 5-2: oscstat: oscillator status register r-1/q r-0/q r-q/q r-0/q r-0/q r-q/q r-0/0 r-0/q t1oscr pllr osts hfiofr hfiofl mfiofr lfiofr hfiofs bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared q = conditional bit 7 t1oscr: timer1 oscillator ready bit if t1oscen = 1 : 1 = timer1 oscillator is ready 0 = timer1 oscillator is not ready if t1oscen = 0 : 1 = timer1 clock source is always ready bit 6 pllr 4x pll ready bit 1 = 4x pll is ready 0 = 4x pll is not ready bit 5 osts: oscillator start-up timer status bit 1 = running from the clock defined by the fosc<2:0> bits of the configuration words 0 = running from an internal oscillator (fosc<2:0> = 100 ) bit 4 hfiofr: high-frequency internal oscillator ready bit 1 = hfintosc is ready 0 = hfintosc is not ready bit 3 hfiofl: high-frequency internal oscillator locked bit 1 = hfintosc is at least 2% accurate 0 = hfintosc is not 2% accurate bit 2 mfiofr: medium-frequency internal oscillator ready bit 1 = mfintosc is ready 0 = mfintosc is not ready bit 1 lfiofr: low-frequency internal oscillator ready bit 1 = lfintosc is ready 0 = lfintosc is not ready bit 0 hfiofs: high-frequency internal oscillator stable bit 1 = hfintosc is at least 0.5% accurate 0 = hfintosc is not 0.5% accurate
pic12(l)f1840 ds41441c-page 56 ? 2011-2012 microchip technology inc. table 5-2: summary of registers asso ciated with clock sources table 5-3: summary of configuration word wi th clock sources register 5-3: osctune: osci llator tuning register u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ? ? tun<5:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 ? bit 5-0 tun<5:0>: frequency tuning bits 100000 = minimum frequency ? ? ? 111111 = 000000 = oscillator module is running at the factory-calibrated frequency. 000001 = ? ? ? 011110 = 011111 = maximum frequency name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page osccon spllen ircf<3:0> ?scs<1:0> 54 oscstat t1oscr pllr osts hfiofr hfiofl mfiofr lfiofr hfiofs 55 osctune ? ?tun<5:0> 56 pie2 osfie ? c1ie eeie bcl1ie ? ? ? 76 pir2 osfif ? c1if eeif bcl1if ? ? ? 78 t1con tmr1cs<1:0> t1ckps<1:0> t1oscen t1sync ? tmr1on 161 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by clock sources. note 1: pic12(l)f1840 only. name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config1 13:8 ? ? fcmen ieso clkouten boren<1:0> cpd 34 7:0 cp mclre pwrte wdte<1:0> fosc<2:0> legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by clock sources. note 1: pic12f1840 only.
? 2011-2012 microchip technology inc. ds41441c-page 57 pic12(l)f1840 6.0 reference clock module the reference clock module provides the ability to send a divided clock to the clock output pin of the device (clkr) and provide a secondary internal clock source to the modulator module. this module is available in all oscillator configurations and allows the user to select a greater range of clock submultiples to drive external devices in the application. the reference clock module includes the following features: ? system clock is the source ? available in all oscillator configurations ? programmable clock divider ? output enable to a port pin ? selectable duty cycle ? slew rate control the reference clock module is controlled by the clkrcon register ( register 6-1 ) and is enabled when setting the clkren bit. to output the divided clock signal to the clkr port pin, the clkroe bit must be set. the clkrdiv<2:0> bits enable the selection of 8 different clock divider options. the clkrdc<1:0> bits can be used to modify the duty cycle of the output clock (1) . the clkrslr bit controls slew rate limiting. for information on using the reference clock output with the modulator module, see section 23.0 ?data signal modulator? . 6.1 slew rate the slew rate limitation on the output port pin can be disabled. the slew rate limitation is removed by clearing the clkrslr bit in the clkrcon register. 6.2 effects of a reset upon any device reset, the reference clock module is disabled. the user?s firmware is responsible for initializing the module before enabling the output. the registers are reset to their default values. 6.3 conflicts with the clkr pin there are two cases when the reference clock output signal cannot be output to the clkr pin, if: ? lp, xt or hs oscillator mode is selected. ? clkout function is enabled. even if either of these cases are true, the module can still be enabled and the reference clock signal may be used in conjunction with the modulator module. 6.3.1 oscillator modes if lp, xt or hs oscillator modes are selected, the osc2/clkr pin must be used as an oscillator input pin and the clkr output cannot be enabled. see section 5.2 ?clock source types? for more informa- tion on different oscillator modes. 6.3.2 clkout function the clkout function has a higher priority than the reference clock module. therefore, if the clkout function is enabled by the clkouten bit in configura- tion words, f osc /4 will always be output on the port pin. reference section 4.0 ?device configuration? for more information. 6.4 operation during sleep as the reference clock module relies on the system clock as its source, and the system clock is disabled in sleep, the module does not function in sleep, even if an external clock source or the timer1 clock source is configured as the system clock. the module outputs will remain in their current state until the device exits sleep. note 1: if the base clock rate is selected without a divider, the output clock will always have a duty cycle equal to that of the source clock, unless a 0% duty cycle is selected. if the clock divider is set to base clock/2, then 25% and 75% duty cycle accuracy will be dependent upon the source clock.
pic12(l)f1840 ds41441c-page 58 ? 2011-2012 microchip technology inc. 6.5 register definition: reference clock control register 6-1: clkrcon: refere nce clock control register r/w-0/0 r/w-0/0 r/w-1/1 r/w-1/1 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 clkren clkroe clkrslr clkrdc<1:0> clkrdiv<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 clkren: reference clock module enable bit 1 = reference clock module is enabled 0 = reference clock module is disabled bit 6 clkroe: reference clock output enable bit (3) 1 = reference clock output is enabled on clkr pin 0 = reference clock output disabled on clkr pin bit 5 clkrslr: reference clock slew rate control limiting enable bit 1 = slew rate limiting is enabled 0 = slew rate limiting is disabled bit 4-3 clkrdc<1:0>: reference clock duty cycle bits 11 = clock outputs duty cycle of 75% 10 = clock outputs duty cycle of 50% 01 = clock outputs duty cycle of 25% 00 = clock outputs duty cycle of 0% bit 2-0 clkrdiv<2:0> reference clock divider bits 111 = base clock value divided by 128 110 = base clock value divided by 64 101 = base clock value divided by 32 100 = base clock value divided by 16 011 = base clock value divided by 8 010 = base clock value divided by 4 001 = base clock value divided by 2 (1) 000 = base clock value (2) note 1: in this mode, the 25% and 75% duty cycle accuracy will be dependent on the source clock duty cycle. 2: in this mode, the duty cycle will always be equal to the source clock duty cycle, unless a duty cycle of 0% is selected. 3: to route clkr to pin, clkouten of configuration words = 1 is required. clkouten of configuration words = 0 will result in f osc /4. see section 6.3 ?conflicts with the clkr pin? for details.
? 2011-2012 microchip technology inc. ds41441c-page 59 pic12(l)f1840 table 6-1: summary of registers associated with reference clock sources table 6-2: summary of co nfiguration word with re ference clock sources name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page clkrcon clkren clkroe clkrslr clkrdc<1:0> clkrdiv <2:0> 58 legend: ? = unimplemented locations read as ? 0 ?. shaded cells are not used by reference clock sources. name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config1 13:8 ? ? fcmen ieso clkouten boren<1:0> cpd 34 7:0 cp mclre pwrte wdte<1:0> fosc<2:0> legend: ? = unimplemented locations read as ? 0 ?. shaded cells are not used by reference clock sources.
pic12(l)f1840 ds41441c-page 60 ? 2011-2012 microchip technology inc. notes:
? 2011-2012 microchip technology inc. ds41441c-page 61 pic12(l)f1840 7.0 resets there are multiple ways to reset this device: ? power-on reset (por) ? brown-out reset (bor) ?mclr reset ?wdt reset ? reset instruction ? stack overflow ? stack underflow ? programming mode exit to a l l o w v dd to stabilize, an optional power-up timer can be enabled to extend the reset time after a bor or por event. a simplified block diagram of the on-chip reset circuit is shown in figure 7-1 . figure 7-1: simplified block di agram of on-chip reset circuit external reset mclr v dd wdt time-out power-on reset lfintosc pwrt 64 ms pwrten brown-out reset bor reset instruction stack pointer stack overflow/underflow reset sleep mclre enable device reset zero programming mode exit
pic12(l)f1840 ds41441c-page 62 ? 2011-2012 microchip technology inc. 7.1 power-on reset (por) the por circuit holds the device in reset until v dd has reached an acceptable level for minimum operation. slow rising v dd , fast operating speeds or analog performance may require greater than minimum v dd . the pwrt, bor or mclr features can be used to extend the start-up period until all device operation conditions have been met. 7.1.1 power-up timer (pwrt) the power-up timer provides a nominal 64 ms time- out on por or brown-out reset. the device is held in reset as long as pwrt is active. the pwrt delay allows additional time for the v dd to rise to an acceptable level. the power-up timer is enabled by clearing the pwrte bit in configuration words. the power-up timer starts after the release of the por and bor. for additional information, refer to application note an607, ?power-up trouble shooting? (ds00607). 7.2 brown-out reset (bor) the bor circuit holds the device in reset when v dd reaches a selectable minimum level. between the por and bor, complete voltage range coverage for execution protection can be implemented. the brown-out reset module has four operating modes controlled by the boren<1:0> bits in configu- ration words. the four operating modes are: ? bor is always on ? bor is off when in sleep ? bor is controlled by software ? bor is always off refer to tab le 7 - 1 for more information. the brown-out reset voltage level is selectable by configuring the borv bit in configuration words. a v dd noise rejection filter prevents the bor from trig- gering on small events. if v dd falls below v bor for a duration greater than parameter t bordc , the device will reset. see figure 7-2 for more information. table 7-1: bor operating modes 7.2.1 bor is always on when the boren bits of configuration words are programmed to ? 11 ?, the bor is always on. the device start-up will be delayed until the bor is ready and v dd is higher than the bor threshold. bor protection is active during sleep. the bor does not delay wake-up from sleep. 7.2.2 bor is off in sleep when the boren bits of configuration words are programmed to ? 10 ?, the bor is on, except in sleep. the device start-up will be delayed until the bor is ready and v dd is higher than the bor threshold. bor protection is not active during sleep. the device wake-up will be delayed until the bor is ready. 7.2.3 bor controlled by software when the boren bits of configuration words are programmed to ? 01 ?, the bor is controlled by the sboren bit of the borcon register. the device start- up is not delayed by the bor ready condition or the v dd level. bor protection begins as soon as the bor circuit is ready. the status of the bor circuit is reflected in the borrdy bit of the borcon register. bor protection is unchanged by sleep. boren<1:0> sboren device mode bor mode instruction execution upon: release of por or wake-up from sleep 11 x x active waits for bor ready (1) (borrdy = 1 ) 10 x awake active waits for bor ready (borrdy = 1 ) sleep disabled 01 1 x active waits for bor ready (1) (borrdy = 1 ) 0 xdisabled begins immediately (borrdy = x ) 00 x xdisabled note 1: in these specific cases, ?release of por? and ?wake-up from sleep?, there is no delay in start-up. the bor ready flag, (borrdy = 1 ), will be set before the cpu is ready to execute instructions because the bor circuit is forced on by the boren<1:0> bits.
? 2011-2012 microchip technology inc. ds41441c-page 63 pic12(l)f1840 figure 7-2: brown -out situations 7.3 register definitions: bor control register 7-1: borco n: brown-out reset control register r/w-1/u r/w-0/u u-0 u-0 u-0 u-0 u-0 r-q/u sboren borfs ? ? ? ? ?borrdy bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared q = value depends on condition bit 7 sboren: software brown-out reset enable bit if boren <1:0> in configuration words ? 01 : sboren is read/write, but has no effect on the bor. if boren <1:0> in configuration words = 01 : 1 = bor enabled 0 = bor disabled bit 6 borfs: brown-out reset fast start bit (1) if boren<1:0> = 11 (always on) or boren<1:0> = 00 (always off) borfs is read/write, but has no effect. if boren <1:0> = 10 (disabled in sleep) or boren<1:0> = 01 (under software control): 1 = band gap is forced on always (covers sleep/wake-up/operating cases) 0 = band gap operates normally, and may turn off bit 5-1 unimplemented: read as ? 0 ? bit 0 borrdy: brown-out reset circuit ready status bit 1 = the brown-out reset circuit is active 0 = the brown-out reset circuit is inactive note 1: boren<1:0> bits are located in configuration words. t pwrt (1) v bor v dd internal reset v bor v dd internal reset t pwrt (1) < t pwrt t pwrt (1) v bor v dd internal reset note 1: t pwrt delay only if pwrte bit is programmed to ? 0 ?.
pic12(l)f1840 ds41441c-page 64 ? 2011-2012 microchip technology inc. 7.4 mclr the mclr is an optional external input that can reset the device. the mclr function is controlled by the mclre bit of configuration words and the lvp bit of configuration words ( table 7-2 ). 7.4.1 mclr enabled when mclr is enabled and the pin is held low, the device is held in reset. the mclr pin is connected to v dd through an internal weak pull-up. the device has a noise filter in the mclr reset path. the filter will detect and ignore small pulses. 7.4.2 mclr disabled when mclr is disabled, the pin functions as a general purpose input and the internal weak pull-up is under software control. see section 12.2 ?porta registers? for more information. 7.5 watchdog timer (wdt) reset the watchdog timer generates a reset if the firmware does not issue a clrwdt instruction within the time-out period. the to and pd bits in the status register are changed to indicate the wdt reset. see section 10.0 ?watchdog timer (wdt)? for more information. 7.6 reset instruction a reset instruction will cause a device reset. the ri bit in the pcon register will be set to ? 0 ?. see ta b l e 7 - 4 for default conditions after a reset instruction has occurred. 7.7 stack overflow/underflow reset the device can reset when the stack overflows or underflows. the stkovf or stkunf bits of the pcon register indicate the reset condition. these resets are enabled by setting the stvren bit in configuration word 2. see section 3.5.2 ?overflow/underflow reset? for more information. 7.8 programming mode exit upon exit of programming mode, the device will behave as if a por had just occurred. 7.9 power-up timer the power-up timer optionally delays device execution after a bor or por event. this timer is typically used to allow v dd to stabilize before allowing the device to start running. the power-up timer is controlled by the pwrte bit of configuration words. 7.10 start-up sequence upon the release of a por or bor, the following must occur before the device will begin executing: 1. power-up timer runs to completion (if enabled). 2. oscillator start-up timer runs to completion (if required for oscillator source). 3. mclr must be released (if enabled). the total time-out will vary based on oscillator configu- ration and power-up timer configuration. see section 5.0 ?oscillator module (with fail-safe clock monitor)? for more information. the power-up timer and oscillator start-up timer run independently of mclr reset. if mclr is kept low long enough, the power-up timer and oscillator start-up timer will expire. upon bringing mclr high, the device will begin execution immediately (see figure 7-3 ). this is useful for testing purposes or to synchronize more than one device operating in parallel. table 7-2: mclr configuration mclre lvp mclr 00 disabled 10 enabled x1 enabled note: a reset does not drive the mclr pin low.
? 2011-2012 microchip technology inc. ds41441c-page 65 pic12(l)f1840 figure 7-3: reset start-up sequence t ost t mclr t pwrt v dd internal por power-up timer mclr internal reset oscillator modes oscillator start-up timer oscillator f osc internal oscillator oscillator f osc external clock (ec) clkin f osc external crystal
pic12(l)f1840 ds41441c-page 66 ? 2011-2012 microchip technology inc. 7.11 determining the cause of a reset upon any reset, multiple bits in the status and pcon register are updated to indicate the cause of the reset. ta b l e 7 - 3 and ta b l e 7 - 4 show the reset condi- tions of these registers. table 7-3: reset status bits and their significance table 7-4: reset condition for special registers stkovf stkunf rmclr ri por bor to pd condition 00110x11 power-on reset 00110x0x illegal, to is set on por 00110xx0 illegal, pd is set on por 0011u011 brown-out reset uuuuuu0u wdt reset uuuuuu00 wdt wake-up from sleep uuuuuu10 interrupt wake-up from sleep uu0uuuuu mclr reset during normal operation uu0uuu10 mclr reset during sleep u u u 0 u u u u reset instruction executed 1uuuuuuu stack overflow reset (stvren = 1 ) u1uuuuuu stack underflow reset (stvren = 1 ) condition program counter status register pcon register power-on reset 0000h ---1 1000 00-- 110x mclr reset during normal operation 0000h ---u uuuu uu-- 0uuu mclr reset during sleep 0000h ---1 0uuu uu-- 0uuu wdt reset 0000h ---0 uuuu uu-- uuuu wdt wake-up from sleep pc + 1 ---0 0uuu uu-- uuuu brown-out reset 0000h ---1 1uuu 00-- 11u0 interrupt wake-up from sleep pc + 1 (1) ---1 0uuu uu-- uuuu reset instruction executed 0000h ---u uuuu uu-- u0uu stack overflow reset (stvren = 1 ) 0000h ---u uuuu 1u-- uuuu stack underflow reset (stvren = 1 ) 0000h ---u uuuu u1-- uuuu legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ? 0 ?. note 1: when the wake-up is due to an interrupt and global enable bit (gie) is set, the return address is pushed on the stack and pc is loaded with the interrupt vector (0004h) after execution of pc + 1.
? 2011-2012 microchip technology inc. ds41441c-page 67 pic12(l)f1840 7.12 power control (pcon) register the power control (pcon) register contains flag bits to differentiate between a: ? power-on reset (por ) ? brown-out reset (bor ) ? reset instruction reset (ri ) ? stack overflow reset (stkovf) ? stack underflow reset (stkunf) ?mclr reset (rmclr ) the pcon register bits are shown in register 7-2 . 7.13 register definitions: power control register 7-2: pcon: power control register r/w/hs-0/q r/w/hs-0/q u-0 u-0 r/w/hc-1/q r/w/hc-1/q r/w/hc-q/u r/w/hc-q/u stkovf stkunf ? ? rmclr ri por bor bit 7 bit 0 legend: hc = bit is cleared by hardware hs = bit is set by hardware r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -m/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared q = value depends on condition bit 7 stkovf: stack overflow flag bit 1 = a stack overflow occurred 0 = a stack overflow has not occurred or set to ? 0 ? by firmware bit 6 stkunf: stack underflow flag bit 1 = a stack underflow occurred 0 = a stack underflow has not occurred or set to ? 0 ? by firmware bit 5-4 unimplemented: read as ? 0 ? bit 3 rmclr : mclr reset flag bit 1 = a mclr reset has not occurred or set to ? 1 ? by firmware 0 = a mclr reset has occurred (set to ? 0 ? in hardware when a mclr reset occurs) bit 2 ri : reset instruction flag bit 1 = a reset instruction has not been executed or set to ? 1 ? by firmware 0 = a reset instruction has been executed (set to ? 0 ? in hardware upon executing a reset instruction) bit 1 por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = no brown-out reset occurred 0 = a brown-out reset occurred (must be set in software after a power-on reset or brown-out reset occurs)
pic12(l)f1840 ds41441c-page 68 ? 2011-2012 microchip technology inc. table 7-5: summary of registers associated with resets name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page borcon sboren borfs ? ? ? ? ? borrdy 63 pcon stkovf stkunf ? ?rmclr ri por bor 67 status ? ? ?to pd z dc c 16 wdtcon ? ? wdtps<4:0> swdten 85 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by resets. note 1: other (non power-up) resets include mclr reset and watchdog timer reset during normal operation.
? 2011-2012 microchip technology inc. ds41441c-page 69 pic12(l)f1840 8.0 interrupts the interrupt feature allows certain events to preempt normal program flow. firmware is used to determine the source of the interrupt and act accordingly. some interrupts can be configured to wake the mcu from sleep mode. this chapter contains the following information for interrupts: ? operation ? interrupt latency ? interrupts during sleep ?int pin ? automatic context saving many peripherals produce interrupts. refer to the corresponding chapters for details. a block diagram of the interrupt logic is shown in figure 8-1 . figure 8-1: interrupt logic tmr0if tmr0ie intf inte iocif iocie interrupt to cpu wake-up (if in sleep mode) gie (tmr1if) pir1<0> pirn<7> peie (tmr1ie) pie1<0> peripheral interrupts pien<7>
pic12(l)f1840 ds41441c-page 70 ? 2011-2012 microchip technology inc. 8.1 operation interrupts are disabled upon any device reset. they are enabled by setting the following bits: ? gie bit of the intcon register ? interrupt enable bit(s) for the specific interrupt event(s) ? peie bit of the intcon register (if the interrupt enable bit of the interrupt event is contained in the piex register) the intcon, pir1 and pir2 registers record individual interrupts via interrupt flag bits. interrupt flag bits will be set, regardless of the status of the gie, peie and individual interrupt enable bits. the following events happen when an interrupt event occurs while the gie bit is set: ? current prefetched instruction is flushed ? gie bit is cleared ? current program counter (pc) is pushed onto the stack ? critical registers are automatically saved to the shadow registers (see section 8.5 ?automatic context saving? ) ? pc is loaded with the interrupt vector 0004h the firmware within the interrupt service routine (isr) should determine the source of the interrupt by polling the interrupt flag bits. the interrupt flag bits must be cleared before exiting the isr to avoid repeated interrupts. because the gie bit is cleared, any interrupt that occurs while executing the isr will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector. the retfie instruction exits the isr by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the gie bit. for additional information on a specific interrupt?s operation, refer to its peripheral chapter. 8.2 interrupt latency interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. the latency for synchronous interrupts is three or four instruction cycles. for asynchronous interrupts, the latency is three to five instruction cycles, depending on when the interrupt occurs. see figure 8-2 and figure 8-3 for more details. note 1: individual interrupt flag bits are set, regardless of the state of any other enable bits. 2: all interrupts will be ignored while the gie bit is cleared. any interrupt occurring while the gie bit is clear will be serviced when the gie bit is set again.
? 2011-2012 microchip technology inc. ds41441c-page 71 pic12(l)f1840 figure 8-2: interrupt latency q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clkout pc 0004h 0005h pc inst(0004h) nop gie q1 q2 q3 q4 q1 q2 q3 q4 1 cycle instruction at pc pc inst(0004h) nop 2 cycle instruction at pc fsr addr pc+1 pc+2 0004h 0005h pc inst(0004h) nop gie pc pc-1 3 cycle instruction at pc execute interrupt inst(pc) interrupt sampled during q1 inst(pc) pc-1 pc+1 nop pc new pc/ pc+1 0005h pc-1 pc+1/fsr addr 0004h nop interrupt gie interrupt inst(pc) nop nop fsr addr pc+1 pc+2 0004h 0005h pc inst(0004h) nop gie pc pc-1 3 cycle instruction at pc interrupt inst(pc) nop nop nop inst(0005h) execute execute execute
pic12(l)f1840 ds41441c-page 72 ? 2011-2012 microchip technology inc. figure 8-3: int pin interrupt timing q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 osc1 clkout int pin intf gie instruction flow pc instruction fetched instruction executed interrupt latency pc pc + 1 pc + 1 0004h 0005h inst (0004h) inst (0005h) dummy cycle inst (pc) inst (pc + 1) inst (pc ? 1) inst (0004h) dummy cycle inst (pc) ? note 1: intf flag is sampled here (every q1). 2: asynchronous interrupt latency = 3-5 t cy . synchronous latency = 3-4 t cy , where t cy = instruction cycle time. latency is the same whether inst (pc) is a single cycle or a 2-cycle instruction. 3: clkout not available in all oscillator modes. 4: for minimum width of int pulse, refer to ac specifications in section 30.0 ?electrical specifications? . 5: intf is enabled to be set any time during the q4-q1 cycles. (1) (2) (3) (4) (5) (1)
? 2011-2012 microchip technology inc. ds41441c-page 73 pic12(l)f1840 8.3 interrupts during sleep some interrupts can be used to wake from sleep. to wake from sleep, the peripheral must be able to operate without the system clock. the interrupt source must have the appropriate interrupt enable bit(s) set prior to entering sleep. on waking from sleep, if the gie bit is also set, the processor will branch to the interrupt vector. otherwise, the processor will continue executing instructions after the sleep instruction. the instruction directly after the sleep instruction will always be executed before branching to the isr. refer to the section 9.0 ?power- down mode (sleep)? for more details. 8.4 int pin the int pin can be used to generate an asynchronous edge-triggered interrupt. this interrupt is enabled by setting the inte bit of the intcon register. the intedg bit of the option_reg register determines on which edge the interrupt will occur. when the intedg bit is set, the rising edge will cause the interrupt. when the intedg bit is clear, the falling edge will cause the interrupt. the intf bit of the intcon register will be set when a valid edge appears on the int pin. if the gie and inte bits are also set, the processor will redirect program execution to the interrupt vector. 8.5 automatic context saving upon entering an interrupt, the return pc address is saved on the stack. additionally, the following registers are automatically saved in the shadow registers: ? w register ? status register (except for to and pd ) ? bsr register ? fsr registers ? pclath register upon exiting the interrupt service routine, these regis- ters are automatically restored. any modifications to these registers during the isr will be lost. if modifica- tions to any of these registers are desired, the corre- sponding shadow register should be modified and the value will be restored when exiting the isr. the shadow registers are available in bank 31 and are readable and writable. depending on the user?s appli- cation, other registers may also need to be saved.
pic12(l)f1840 ds41441c-page 74 ? 2011-2012 microchip technology inc. 8.6 register definitions: interrupt control register 8-1: intcon: interrupt control register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r-0/0 gie peie tmr0ie inte iocie tmr0if intf iocif bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 gie: global interrupt enable bit 1 = enables all active interrupts 0 = disables all interrupts bit 6 peie: peripheral interrupt enable bit 1 = enables all active peripheral interrupts 0 = disables all peripheral interrupts bit 5 tmr0ie: timer0 overflow interrupt enable bit 1 = enables the timer0 interrupt 0 = disables the timer0 interrupt bit 4 inte: int external interrupt enable bit 1 = enables the int external interrupt 0 = disables the int external interrupt bit 3 iocie: interrupt-on-change enable bit 1 = enables the interrupt-on-change 0 = disables the interrupt-on-change bit 2 tmr0if: timer0 overflow interrupt flag bit 1 = tmr0 register has overflowed 0 = tmr0 register did not overflow bit 1 intf: int external interrupt flag bit 1 = the int external interrupt occurred 0 = the int external interrupt did not occur bit 0 iocif: interrupt-on-change interrupt flag bit (1) 1 = when at least one of the interrupt-on-change pins changed state 0 = none of the interrupt-on-change pins have changed state note 1: the iocif flag bit is read-only and cleared when all the interrupt-on-change flags in the iocaf register have been cleared by software. note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie, of the intcon register. user software should ensure the appropri- ate interrupt flag bits are clear prior to enabling an interrupt.
? 2011-2012 microchip technology inc. ds41441c-page 75 pic12(l)f1840 register 8-2: pie1: peripheral interrupt enable register 1 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 tmr1gie adie rcie txie ssp1ie ccp1ie tmr2ie tmr1ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 tmr1gie: timer1 gate interrupt enable bit 1 = enables the timer1 gate acquisition interrupt 0 = disables the timer1 gate acquisition interrupt bit 6 adie: analog-to-digital converter (adc) interrupt enable bit 1 = enables the adc interrupt 0 = disables the adc interrupt bit 5 rcie: usart receive interrupt enable bit 1 = enables the usart receive interrupt 0 = disables the usart receive interrupt bit 4 txie: usart transmit interrupt enable bit 1 = enables the usart transmit interrupt 0 = disables the usart transmit interrupt bit 3 ssp1ie: synchronous serial port (mssp) interrupt enable bit 1 = enables the mssp interrupt 0 = disables the mssp interrupt bit 2 ccp1ie: ccp1 interrupt enable bit 1 = enables the ccp1 interrupt 0 = disables the ccp1 interrupt bit 1 tmr2ie: tmr2 to pr2 match interrupt enable bit 1 = enables the timer2 to pr2 match interrupt 0 = disables the timer2 to pr2 match interrupt bit 0 tmr1ie: timer1 overflow interrupt enable bit 1 = enables the timer1 overflow interrupt 0 = disables the timer1 overflow interrupt note: bit peie of the intcon register must be set to enable any peripheral interrupt.
pic12(l)f1840 ds41441c-page 76 ? 2011-2012 microchip technology inc. register 8-3: pie2: peripheral interrupt enable register 2 r/w-0/0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 u-0 u-0 osfie ? c1ie eeie bcl1ie ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 osfie: oscillator fail interrupt enable bit 1 = enables the oscillator fail interrupt 0 = disables the oscillator fail interrupt bit 6 unimplemented: read as ? 0 ? bit 5 c1ie: comparator c1 interrupt enable bit 1 = enables the comparator c1 interrupt 0 = disables the comparator c1 interrupt bit 4 eeie: eeprom write completion interrupt enable bit 1 = enables the eeprom write completion interrupt 0 = disables the eeprom write completion interrupt bit 3 bcl1ie: mssp bus collision interrupt enable bit 1 = enables the mssp bus collision interrupt 0 = disables the mssp bus collision interrupt bit 2-0 unimplemented: read as ? 0 ? note: bit peie of the intcon register must be set to enable any peripheral interrupt.
? 2011-2012 microchip technology inc. ds41441c-page 77 pic12(l)f1840 register 8-4: pir1: peripheral interrupt request register 1 r/w-0/0 r/w-0/0 r-0/0 r-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 tmr1gif adif rcif txif ssp1if ccp1if tmr2if tmr1if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 tmr1gif: timer1 gate interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 6 adif: adc interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 5 rcif: usart receive interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 4 txif: usart transmit interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 3 ssp1if: synchronous serial port (mssp) interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 2 ccp1if: ccp1 interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 1 tmr2if: timer2 to pr2 interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 0 tmr1if: timer1 overflow interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie, of the intcon register. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
pic12(l)f1840 ds41441c-page 78 ? 2011-2012 microchip technology inc. table 8-1: summary of registers associated with interrupts register 8-5: pir2: peripheral interrupt request register 2 r/w-0/0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 u-0 u-0 osfif ? c1if eeif bcl1if ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 osfif: oscillator fail interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 6 unimplemented: read as ? 0 ? bit 5 c1if: comparator c1 interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 4 eeif: eeprom write completion interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 3 bcl1if: mssp bus collision interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 2-0 unimplemented: read as ? 0 ? note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie, of the intcon register. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie peie tmr0ie inte iocie tmr0if intf iocif 74 option_reg wpuen intedg tmr0cs tmr0se psa ps<2:0> 151 pie1 tmr1gie adie rcie txie ssp1ie ccp1ie tmr2ie tmr1ie 75 pie2 osfie ? c1ie eeie bcl1ie ? ? ? 76 pir1 tmr1gif adif rcif txif ssp1if ccp1if tmr2if tmr1if 77 pir2 osfif ? c1if eeif bcl1if ? ? ? 78 legend: ? = unimplemented locations read as ? 0 ?. shaded cells are not used by interrupts.
? 2011-2012 microchip technology inc. ds41441c-page 79 pic12(l)f1840 9.0 power-down mode (sleep) the power-down mode is entered by executing a sleep instruction. upon entering sleep mode, the following conditions exist: 1. wdt will be cleared but keeps running, if enabled for operation during sleep. 2. pd bit of the status register is cleared. 3. to bit of the status register is set. 4. cpu clock is disabled. 5. 31 khz lfintosc is unaffected and peripherals that operate from it may continue operation in sleep. 6. timer1 and peripherals that operate from timer1 continue operation in sleep when the timer1 clock source selected is: ?lfintosc ?t1cki ? timer1 oscillator ? capsense oscillator 7. adc is unaffected, if the dedicated f rc oscillator is selected. 8. capacitive sensing oscillator is unaffected. 9. i/o ports maintain the status they had before sleep was executed (driving high, low or high- impedance). 10. resets other than wdt are not affected by sleep mode. refer to individual chapters for more details on peripheral operation during sleep. to minimize current consumption, the following condi- tions should be considered: ? i/o pins should not be floating ? external circuitry sinking current from i/o pins ? internal circuitry sourcing current from i/o pins ? current draw from pins with internal weak pull-ups ? modules using 31 khz lfintosc ? modules using timer1 oscillator i/o pins that are high-impedance inputs should be pulled to v dd or v ss externally to avoid switching currents caused by floating inputs. examples of internal circuitry that might be sourcing current include modules such as the dac and fvr modules. see section 17.0 ?digital-to-analog converter (dac) module? and section 14.0 ?fixed voltage reference (fvr)? for more information on these modules. 9.1 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. external reset input on mclr pin, if enabled 2. bor reset, if enabled 3. por reset 4. watchdog timer, if enabled 5. any external interrupt 6. interrupts by peripherals capable of running dur- ing sleep (see individual peripheral for more information) the first three events will cause a device reset. the last three events are considered a continuation of pro- gram execution. to determine whether a device reset or wake-up event occurred, refer to section 7.11 ?determining the cause of a reset? . when the sleep instruction is being executed, the next instruction (pc + 1) is prefetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be enabled. wake-up will occur regardless of the state of the gie bit. if the gie bit is disabled, the device continues execution at the instruction after the sleep instruction. if the gie bit is enabled, the device executes the instruction after the sleep instruction, the device will then call the interrupt service routine. in cases where the execution of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. the wdt is cleared when the device wakes up from sleep, regardless of the source of wake-up.
pic12(l)f1840 ds41441c-page 80 ? 2011-2012 microchip technology inc. 9.1.1 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: ? if the interrupt occurs before the execution of a sleep instruction - sleep instruction will execute as a nop . - wdt and wdt prescaler will not be cleared -to bit of the status register will not be set -pd bit of the status register will not be cleared. ? if the interrupt occurs during or after the execu- tion of a sleep instruction - sleep instruction will be completely exe- cuted - device will immediately wake-up from sleep - wdt and wdt prescaler will be cleared -to bit of the status register will be set -pd bit of the status register will be cleared. even if the flag bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as a nop . figure 9-1: wake-up from sleep through interrupt q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 (1) clkout (2) interrupt flag gie bit (intcon reg.) instruction flow pc instruction fetched instruction executed pc pc + 1 pc + 2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency (4) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) forced nop pc + 2 0004h 0005h forced nop t1 osc (3) pc + 2 note 1: xt, hs or lp oscillator mode assumed. 2: clkout is shown here for timing reference. 3: t1 osc ; see section 30.0 ?electrical specifications? . 4: gie = 1 assumed. in this case after wake-up, the processor calls the isr at 0004h. if gie = 0 , execution will continue in-line.
? 2011-2012 microchip technology inc. ds41441c-page 81 pic12(l)f1840 9.2 low-power sleep mode the pic12f1840 device contains an internal low dropout (ldo) voltage regulator, which allows the device i/o pins to operate at voltages up to 5.5v while the internal device logic operates at a lower voltage. the ldo and its associated reference circuitry must remain active when the device is in sleep mode. the pic12f1840 allows the user to optimize the operating current in sleep, depending on the application require- ments. a low-power sleep mode can be selected by setting the vregpm bit of the vregcon register. with this bit set, the ldo and reference circuitry are placed in a low-power state when the device is in sleep. 9.2.1 sleep current vs. wake-up time in the default operating mode, the ldo and reference circuitry remain in the normal configuration while in sleep. the device is able to exit sleep mode quickly since all circuits remain active. in low-power sleep mode, when waking up from sleep, an extra delay time is required for these circuits to return to the normal con- figuration and stabilize. the low-power sleep mode is beneficial for applica- tions that stay in sleep mode for long periods of time. the normal mode is beneficial for applications that need to wake from sleep quickly and frequently. 9.2.2 peripheral usage in sleep some peripherals that can operate in sleep mode will not operate properly with the low-power sleep mode selected. the ldo will remain in the normal power mode when those peripherals are enabled. the low- power sleep mode is intended for use with these peripherals: ? brown-out reset (bor) ? watchdog timer (wdt) ? external interrupt pin/interrupt-on-change pins ? timer1 (with external clock source) ? comparator ? eccp (capture mode) note: the pic12lf1840 does not have a con- figurable low-power sleep mode. pic12lf1840 is an unregulated device and is always in the lowest power state when in sleep, with no wake-up time pen- alty. this device has a lower maximum v dd and i/o voltage than the pic12f1840. see section 30.0 ?electri- cal specifications? for more information.
pic12(l)f1840 ds41441c-page 82 ? 2011-2012 microchip technology inc. 9.3 register definitions: voltage regulator control table 9-1: summary of registers as sociated with power-down mode register 9-1: vregcon: voltag e regulator control register (1) u-0 u-0 u-0 u-0 u-0 u-0 r/w-0/0 r/w-1/1 ? ? ? ? ? ?vregpm reserved bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-2 unimplemented: read as ? 0 ? bit 1 vregpm: voltage regulator power mode selection bit 1 = low-power sleep mode enabled in sleep (2) draws lowest current in sleep, slower wake-up 0 = normal-power mode enabled in sleep (2) draws higher current in sleep, faster wake-up bit 0 reserved: read as ? 1 ?. maintain this bit set. note 1: pic12f1840 only. 2: see section 30.0 ?electrical specifications? . name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie peie tmr0ie inte iocie tmr0if intf iocif 74 iocaf ? ? iocaf5 iocaf4 iocaf3 iocaf2 iocaf1 iocaf0 111 iocan ? ? iocan5 iocan4 iocan3 iocan2 iocan1 iocan0 111 iocap ? ? iocap5 iocap4 iocap3 iocap2 iocap1 iocap0 111 pie1 tmr1gie adie rcie txie ssp1ie ccp1ie tmr2ie tmr1ie 75 pie2 osfie ?c1ieeeie bcl1ie ? ? ? 76 pir1 tmr1gif adif rcif txif ssp1if ccp1if tmr2if tmr1if 77 pir2 osfif ?c1ifeeif bcl1if ? ? ? 78 status ? ? ?to pd z dc c 16 vregcon (1) ? ? ? ? ? ?vregpm reserved 82 wdtcon ? ?wdtps<4:0>swdten 85 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used in power-down mode. note 1: pic12f1840 only.
? 2011-2012 microchip technology inc. ds41441c-page 83 pic12(l)f1840 10.0 watchdog timer (wdt) the watchdog timer is a system timer that generates a reset if the firmware does not issue a clrwdt instruction within the time-out period. the watchdog timer is typically used to recover the system from unexpected events. the wdt has the following features: ? independent clock source ? multiple operating modes - wdt is always on - wdt is off when in sleep - wdt is controlled by software - wdt is always off ? configurable time-out period is from 1 ms to 256 seconds (nominal) ? multiple reset conditions ? operation during sleep figure 10-1: watchdog ti mer block diagram lfintosc 23-bit programmable prescaler wdt wdt time-out wdtps<4:0> swdten sleep wdte<1:0> = 11 wdte<1:0> = 01 wdte<1:0> = 10
pic12(l)f1840 ds41441c-page 84 ? 2011-2012 microchip technology inc. 10.1 independent clock source the wdt derives its time base from the 31 khz lfintosc internal oscillator. time intervals in this chapter are based on a nominal interval of 1 ms. see section 30.0 ?electrical specifications? for the lfintosc tolerances. 10.2 wdt operating modes the watchdog timer module has four operating modes controlled by the wdte<1:0> bits in configuration words. see table 10-1 . 10.2.1 wdt is always on when the wdte bits of configuration words are set to ? 11 ?, the wdt is always on. wdt protection is active during sleep. 10.2.2 wdt is off in sleep when the wdte bits of configuration words are set to ? 10 ?, the wdt is on, except in sleep. wdt protection is not active during sleep. 10.2.3 wdt controlled by software when the wdte bits of configuration words are set to ? 01 ?, the wdt is controlled by the swdten bit of the wdtcon register. wdt protection is unchanged by sleep. see table 10-1 for more details. table 10-1: wdt operating modes 10.3 time-out period the wdtps bits of the wdtcon register set the time-out period from 1 ms to 256 seconds (nominal). after a reset, the default time-out period is two seconds. 10.4 clearing the wdt the wdt is cleared when any of the following condi- tions occur: ?any reset ? clrwdt instruction is executed ? device enters sleep ? device wakes up from sleep ? oscillator fail ? wdt is disabled ?ost is running see table 10-2 for more information. 10.5 operation during sleep when the device enters sleep, the wdt is cleared. if the wdt is enabled during sleep, the wdt resumes counting. when the device exits sleep, the wdt is cleared again. the wdt remains clear until the ost, if enabled, completes. see section 5.0 ?oscillator module (with fail-safe clock monitor)? for more information on the ost. when a wdt time-out occurs while the device is in sleep, no reset is generated. instead, the device wakes up and resumes operation. the to and pd bits in the status register are changed to indicate the event. see section 3.0 ?memory organization? and the status register ( register 3-1 ) for more information. wdte<1:0> swdten device mode wdt mode 11 x xactive 10 x awake active sleep disabled 01 1 xactive 0 x disabled 00 x x disabled table 10-2: wdt clearing conditions conditions wdt wdte<1:0> = 00 cleared wdte<1:0> = 01 and swdten = 0 wdte<1:0> = 10 and enter sleep clrwdt command oscillator fail detected exit sleep + system clock = t1osc, extrc, intosc, extclk exit sleep + system clock = xt, hs, lp cleared until the end of ost change intosc divider (ircf bits) unaffected
? 2011-2012 microchip technology inc. ds41441c-page 85 pic12(l)f1840 10.6 register definitions: watchdog control register 10-1: wdtcon: wat chdog timer control register u-0 u-0 r/w-0/0 r/w-1/1 r/w-0/0 r/w-1/1 r/w-1/1 r/w-0/0 ? ? wdtps<4:0> swdten bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -m/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 ? bit 5-1 wdtps<4:0>: watchdog timer period select bits bit value = prescale rate 11111 = reserved. results in minimum interval (1:32) ? ? ? 10011 = reserved. results in minimum interval (1:32) 10010 = 1:8388608 (2 23 ) (interval 256s nominal) 10001 = 1:4194304 (2 22 ) (interval 128s nominal) 10000 = 1:2097152 (2 21 ) (interval 64s nominal) 01111 = 1:1048576 (2 20 ) (interval 32s nominal) 01110 = 1:524288 (2 19 ) (interval 16s nominal) 01101 = 1:262144 (2 18 ) (interval 8s nominal) 01100 = 1:131072 (2 17 ) (interval 4s nominal) 01011 = 1:65536 (interval 2s nominal) (reset value) 01010 = 1:32768 (interval 1s nominal) 01001 = 1:16384 (interval 512 ms nominal) 01000 = 1:8192 (interval 256 ms nominal) 00111 = 1:4096 (interval 128 ms nominal) 00110 = 1:2048 (interval 64 ms nominal) 00101 = 1:1024 (interval 32 ms nominal) 00100 = 1:512 (interval 16 ms nominal) 00011 = 1:256 (interval 8 ms nominal) 00010 = 1:128 (interval 4 ms nominal) 00001 = 1:64 (interval 2 ms nominal) 00000 = 1:32 (interval 1 ms nominal) bit 0 swdten: software enable/disable for watchdog timer bit if wdte<1:0> = 00 : this bit is ignored. if wdte<1:0> = 01 : 1 = wdt is turned on 0 = wdt is turned off if wdte<1:0> = 1x : this bit is ignored.
pic12(l)f1840 ds41441c-page 86 ? 2011-2012 microchip technology inc. table 10-3: summary of registers associated with watchdog timer table 10-4: summary of configurat ion word with watchdog timer name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page osccon spllen ircf<3:0> ?scs<1:0> 54 status ? ? ?to pd z dc c 16 wdtcon ? ? wdtps<4:0> swdten 85 legend: x = unknown, u = unchanged, ? = unimplemented locations read as ? 0 ?. shaded cells are not used by watchdog timer . name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config1 13:8 ? ? fcmen ieso clkouten boren<1:0> ? 34 7:0 cp mclre pwrte wdte<1:0> fosc<2:0> legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by watchdog timer.
? 2011-2012 microchip technology inc. ds41441c-page 87 pic12(l)f1840 11.0 data eeprom and flash program memory control the data eeprom and flash program memory are readable and writable during normal operation (full v dd range). these memories are not directly mapped in the register file space. instead, they are indirectly addressed through the special function registers (sfrs). there are six sfrs used to access these memories: ? eecon1 ? eecon2 ? eedatl ?eedath ? eeadrl ?eeadrh when interfacing the data memory block, eedatl holds the 8-bit data for read/write, and eeadrl holds the address of the eedatl location being accessed. these devices have 256 bytes of data eeprom with an address range from 0h to 0ffh. when accessing the program memory block, the eed- ath:eedatl register pair forms a 2-byte word that holds the 14-bit data for read/write, and the eeadrl and eeadrh registers form a 2-byte word that holds the 15-bit address of the program memory location being read. the eeprom data memory allows byte read and write. an eeprom byte write automatically erases the loca- tion and writes the new data (erase before write). the write time is controlled by an on-chip timer. the write/erase voltages are generated by an on-chip charge pump rated to operate over the voltage range of the device for byte or word operations. depending on the setting of the flash program memory self write enable bits wrt<1:0> of the configuration words, the device may or may not be able to write certain blocks of the program memory. however, reads from the program memory are always allowed. when the device is code-protected, the device programmer can no longer access data or program memory. when code-protected, the cpu may continue to read and write the data eeprom memory and flash program memory. 11.1 eeadrl and eeadrh registers the eeadrh:eeadrl register pair can address up to a maximum of 256 bytes of data eeprom or up to a maximum of 32k words of program memory. when selecting a program address value, the msb of the address is written to the eeadrh register and the lsb is written to the eeadrl register. when selecting a eeprom address value, only the lsb of the address is written to the eeadrl register. 11.1.1 eecon1 and eecon2 registers eecon1 is the control register for ee memory accesses. control bit eepgd determines if the access will be a program or data memory access. when clear, any subsequent operations will operate on the eeprom memory. when set, any subsequent operations will operate on the program memory. on reset, eeprom is selected by default. control bits rd and wr initiate read and write, respectively. these bits cannot be cleared, only set, in software. they are cleared in hardware at completion of the read or write operation. the inability to clear the wr bit in software prevents the accidental, premature termination of a write operation. the wren bit, when set, will allow a write operation to occur. on power-up, the wren bit is clear. the wrerr bit is set when a write operation is interrupted by a reset during normal operation. in these situations, following reset, the user can check the wrerr bit and execute the appropriate error handling routine. interrupt flag bit eeif of the pir2 register is set when write is complete. it must be cleared in the software. reading eecon2 will read all ? 0 ?s. the eecon2 reg- ister is used exclusively in the data eeprom write sequence. to enable writes, a specific pattern must be written to eecon2.
pic12(l)f1840 ds41441c-page 88 ? 2011-2012 microchip technology inc. 11.2 using the data eeprom the data eeprom is a high-endurance, byte address- able array that has been optimized for the storage of frequently changing information (e.g., program vari- ables or other data that are updated often). when vari- ables in one section change frequently, while variables in another section do not change, it is possible to exceed the total number of write cycles to the eeprom without exceeding the total number of write cycles to a single byte. refer to section 30.0 ?electri- cal specifications? . if this is the case, then a refresh of the array must be performed. for this reason, vari- ables that change infrequently (such as constants, ids, calibration, etc.) should be stored in flash program memory. 11.2.1 reading the data eeprom memory to read a data memory location, the user must write the address to the eeadrl register, clear the eepgd and cfgs control bits of the eecon1 register, and then set control bit rd. the data is available at the very next cycle, in the eedatl register; therefore, it can be read in the next instruction. eedatl will hold this value until another read or until it is written to by the user (during a write operation). example 11-1: data eeprom read 11.2.2 writing to the data eeprom memory to write an eeprom data location, the user must first write the address to the eeadrl register and the data to the eedatl register. then the user must follow a specific sequence to initiate the write for each byte. the write will not initiate if the above sequence is not followed exactly (write 55h to eecon2, write aah to eecon2, then set the wr bit) for each byte. interrupts should be disabled during this code segment. additionally, the wren bit in eecon1 must be set to enable write. this mechanism prevents accidental writes to data eeprom due to errant (unexpected) code execution (i.e., lost programs). the user should keep the wren bit clear at all times, except when updating eeprom. the wren bit is not cleared by hardware. after a write sequence has been initiated, clearing the wren bit will not affect this write cycle. the wr bit will be inhibited from being set unless the wren bit is set. at the completion of the write cycle, the wr bit is cleared in hardware and the ee write complete interrupt flag bit (eeif) is set. the user can either enable this interrupt or poll this bit. eeif must be cleared by software. 11.2.3 protection against spurious write there are conditions when the user may not want to write to the data eeprom memory. to protect against spurious eeprom writes, various mechanisms have been built-in. on power-up, wren is cleared. also, the power-up timer (64 ms duration) prevents eeprom write. the write initiate sequence and the wren bit together help prevent an accidental write during: ? brown-out ? power glitch ? software malfunction 11.2.4 data eeprom operation during code-protect data memory can be code-protected by programming the cpd bit in the configuration words to ? 0 ?. when the data memory is code-protected, only the cpu is able to read and write data to the data eeprom. it is recommended to code-protect the pro- gram memory when code-protecting data memory. this prevents anyone from replacing your program with a program that will access the contents of the data eeprom. note: data eeprom can be read regardless of the setting of the cpd bit. banksel eeadrl ; movlw data_ee_addr ; movwf eeadrl ;data memory ;address to read bcf eecon1, cfgs ;deselect config space bcf eecon1, eepgd;point to data memory bsf eecon1, rd ;ee read movf eedatl, w ;w = eedatl
? 2011-2012 microchip technology inc. ds41441c-page 89 pic12(l)f1840 example 11-2: data eeprom write figure 11-1: flash program me mory read cycle execution banksel eeadrl ; movlw data_ee_addr ; movwf eeadrl ;data memory address to write movlw data_ee_data ; movwf eedatl ;data memory value to write bcf eecon1, cfgs ;deselect configuration space bcf eecon1, eepgd ;point to data memory bsf eecon1, wren ;enable writes bcf intcon, gie ;disable ints. movlw 55h ; movwf eecon2 ;write 55h movlw 0aah ; movwf eecon2 ;write aah bsf eecon1, wr ;set wr bit to begin write bsf intcon, gie ;enable interrupts bcf eecon1, wren ;disable writes btfsc eecon1, wr ;wait for write to complete goto $-2 ;done required sequence q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 bsf eecon1,rd executed here instr(pc + 1) executed here forced nop executed here pc pc + 1 eeadrh,eeadrl pc+3 pc + 5 flash addr rd bit eedath,eedatl pc + 3 pc + 4 instr (pc + 1) instr(pc - 1) executed here instr(pc + 3) executed here instr(pc + 4) executed here flash data eedath eedatl register instr (pc) instr (pc + 3) instr (pc + 4)
pic12(l)f1840 ds41441c-page 90 ? 2011-2012 microchip technology inc. 11.3 flash program memory overview it is important to understand the flash program mem- ory structure for erase and programming operations. flash program memory is arranged in rows. a row con- sists of a fixed number of 14-bit program memory words. a row is the minimum block size that can be erased by user software. flash program memory may only be written or erased if the destination address is in a segment of memory that is not write-protected, as defined in bits wrt<1:0> of configuration words. after a row has been erased, the user can reprogram all or a portion of this row. data to be written into the program memory row is written to 14-bit wide data write latches. these write latches are not directly accessible to the user, but may be loaded via sequential writes to the eedath:eedatl register pair. the number of data write latches may not be equivalent to the number of row locations. during programming, user software may need to fill the set of write latches and initiate a programming operation multiple times in order to fully reprogram an erased row. for example, a device with a row size of 32 words and eight write latches will need to load the write latches with data and initiate a programming operation four times. the size of a program memory row and the number of program memory write latches may vary by device. see table 11-1 for details. 11.3.1 reading the flash program memory to read a program memory location, the user must: 1. write the least and most significant address bits to the eeadrh:eeadrl register pair. 2. clear the cfgs bit of the eecon1 register. 3. set the eepgd control bit of the eecon1 register. 4. then, set control bit rd of the eecon1 register. once the read control bit is set, the program memory flash controller will use the second instruction cycle to read the data. this causes the second instruction immediately following the ? bsf eecon1,rd ? instruction to be ignored. the data is available in the very next cycle, in the eedath:eedatl register pair; therefore, it can be read as two bytes in the following instructions. eedath:eedatl register pair will hold this value until another read or until it is written to by the user. note: if the user wants to modify only a portion of a previously programmed row, then the contents of the entire row must be read and saved in ram prior to the erase. table 11-1: flash memory organization by device device erase block (row) size/ boundary number of write latches/ boundary pic12(l)f1840 32 words, eeadrl<4:0> = 00000 32 words, eeadrl<4:0> = 00000 note 1: the two instructions following a program memory read are required to be nop s. this prevents the user from executing a two-cycle instruction on the next instruction after the rd bit is set. 2: flash program memory can be read regardless of the setting of the cp bit.
? 2011-2012 microchip technology inc. ds41441c-page 91 pic12(l)f1840 example 11-3: flash program memory read * this code block will read 1 word of program * memory at the memory address: prog_addr_hi: prog_addr_lo * data will be returned in the variables; * prog_data_hi, prog_data_lo banksel eeadrl ; select bank for eeprom registers movlw prog_addr_lo ; movwf eeadrl ; store lsb of address movlw prog_addr_hi ; movwl eeadrh ; store msb of address bcf eecon1,cfgs ; do not select configuration space bsf eecon1,eepgd ; select program memory bcf intcon,gie ; disable interrupts bsf eecon1,rd ; initiate read nop ; executed ( figure 11-1 ) nop ; ignored ( figure 11-1 ) bsf intcon,gie ; restore interrupts movf eedatl,w ; get lsb of word movwf prog_data_lo ; store in user location movf eedath,w ; get msb of word movwf prog_data_hi ; store in user location
pic12(l)f1840 ds41441c-page 92 ? 2011-2012 microchip technology inc. 11.3.2 erasing flash program memory while executing code, program memory can only be erased by rows. to erase a row: 1. load the eeadrh:eeadrl register pair with the address of new row to be erased. 2. clear the cfgs bit of the eecon1 register. 3. set the eepgd, free and wren bits of the eecon1 register. 4. write 55h, then aah, to eecon2 (flash programming unlock sequence). 5. set control bit wr of the eecon1 register to begin the erase operation. 6. poll the free bit in the eecon1 register to determine when the row erase has completed. see example 11-4 . after the ? bsf eecon1,wr ? instruction, the processor requires two cycles to set up the erase operation. the user must place two nop instructions after the wr bit is set. the processor will halt internal operations for the typical 2 ms erase time. this is not sleep mode as the clocks and peripherals will continue to run. after the erase cycle, the processor will resume operation with the third instruction after the eecon1 write instruction. 11.3.3 writing to flash program memory program memory is programmed using the following steps: 1. load the starting address of the word(s) to be programmed. 2. load the write latches with data. 3. initiate a programming operation. 4. repeat steps 1 through 3 until all data is written. before writing to program memory, the word(s) to be written must be erased or previously unwritten. pro- gram memory can only be erased one row at a time. no automatic erase occurs upon the initiation of the write. program memory can be written one or more words at a time. the maximum number of words written at one time is equal to the number of write latches. see figure 11-2 (block writes to program memory with 32 write latches) for more details. the write latches are aligned to the address boundary defined by eeadrl as shown in ta b l e 11 - 1 . write operations do not cross these boundaries. at the completion of a program memory write operation, the write latches are reset to contain 0x3fff. the following steps should be completed to load the write latches and program a block of program memory. these steps are divided into two parts. first, all write latches are loaded with data except for the last program memory location. then, the last write latch is loaded and the programming sequence is initiated. a special unlock sequence is required to load a write latch with data or initiate a flash programming operation. this unlock sequence should not be interrupted. 1. set the eepgd and wren bits of the eecon1 register. 2. clear the cfgs bit of the eecon1 register. 3. set the lwlo bit of the eecon1 register. when the lwlo bit of the eecon1 register is ? 1 ?, the write sequence will only load the write latches and will not initiate the write to flash program memory. 4. load the eeadrh:eeadrl register pair with the address of the location to be written. 5. load the eedath:eedatl register pair with the program memory data to be written. 6. write 55h, then aah, to eecon2, then set the wr bit of the eecon1 register (flash programming unlock sequence). the write latch is now loaded. 7. increment the eeadrh:eeadrl register pair to point to the next location. 8. repeat steps 5 through 7 until all but the last write latch has been loaded. 9. clear the lwlo bit of the eecon1 register. when the lwlo bit of the eecon1 register is ? 0 ?, the write sequence will initiate the write to flash program memory. 10. load the eedath:eedatl register pair with the program memory data to be written. 11. write 55h, then aah, to eecon2, then set the wr bit of the eecon1 register (flash programming unlock sequence). the entire latch block is now written to flash program memory. it is not necessary to load the entire write latch block with user program data. however, the entire write latch block will be written to program memory. an example of the complete write sequence for 32 words is shown in example 11-5 . the initial address is loaded into the eeadrh:eeadrl register pair; the 32 words of data are loaded using indirect addressing.
? 2011-2012 microchip technology inc. ds41441c-page 93 pic12(l)f1840 after the ? bsf eecon1,wr ? instruction, the processor requires two cycles to set up the write operation. the user must place two nop instructions after the wr bit is set. the processor will halt internal operations for the typical 2 ms, only during the cycle in which the write takes place (i.e., the last word of the block write). this is not sleep mode as the clocks and peripherals will continue to run. the processor does not stall when lwlo = 1 , loading the write latches. after the write cycle, the processor will resume operation with the third instruction after the eecon1 write instruction. figure 11-2: block writes to flash program memory with 32 write latches example 11-4: erasing one row of program memory 14 14 14 14 program memory buffer register eeadrl<4:0> = 00000 buffer register eeadrl<4:0> = 00001 buffer register eeadrl<4:0> = 00010 buffer register eeadrl<4:0> = 11111 eedata eedath 75 07 0 6 8 first word of block to be written last word of block to be written ; this row erase routine assumes the following: ; 1. a valid address within the erase block is loaded in addrh:addrl ; 2. addrh and addrl are located in shared data memory 0x70 - 0x7f bcf intcon,gie ; disable ints so required sequences will execute properly banksel eeadrl movf addrl,w ; load lower 8 bits of erase address boundary movwf eeadrl movf addrh,w ; load upper 6 bits of erase address boundary movwf eeadrh bsf eecon1,eepgd ; point to program memory bcf eecon1,cfgs ; not configuration space bsf eecon1,free ; specify an erase operation bsf eecon1,wren ; enable writes movlw 55h ; start of required sequence to initiate erase movwf eecon2 ; write 55h movlw 0aah ; movwf eecon2 ; write aah bsf eecon1,wr ; set wr bit to begin erase nop ; any instructions here are ignored as processor ; halts to begin erase sequence nop ; processor will stop here and wait for erase complete. ; after erase processor continues with 3rd instruction bcf eecon1,wren ; disable writes bsf intcon,gie ; enable interrupts required sequence
pic12(l)f1840 ds41441c-page 94 ? 2011-2012 microchip technology inc. example 11-5: writing to flash program memory ; this write routine assumes the following: ; 1. the 64 bytes of data are loaded, starting at the address in data_addr ; 2. each word of data to be written is made up of two adjacent bytes in data_addr, ; stored in little endian format ; 3. a valid starting address (the least significant bits = 00000) is loaded in addrh:addrl ; 4. addrh and addrl are located in shared data memory 0x70 - 0x7f ; bcf intcon,gie ; disable ints so required sequences will execute properly banksel eeadrh ; bank 3 movf addrh,w ; load initial address movwf eeadrh ; movf addrl,w ; movwf eeadrl ; movlw low data_addr ; load initial data address movwf fsr0l ; movlw high data_addr ; load initial data address movwf fsr0h ; bsf eecon1,eepgd ; point to program memory bcf eecon1,cfgs ; not configuration space bsf eecon1,wren ; enable writes bsf eecon1,lwlo ; only load write latches loop moviw fsr0++ ; load first data byte into lower movwf eedatl ; moviw fsr0++ ; load second data byte into upper movwf eedath ; movf eeadrl,w ; check if lower bits of address are '00000' xorlw 0x1f ; check if we're on the last of 32 addresses andlw 0x1f ; btfsc status,z ; exit if last of 32 words, goto start_write ; movlw 55h ; start of required write sequence: movwf eecon2 ; write 55h movlw 0aah ; movwf eecon2 ; write aah bsf eecon1,wr ; set wr bit to begin write nop ; any instructions here are ignored as processor ; halts to begin write sequence nop ; processor will stop here and wait for write to complete. ; after write processor continues with 3rd instruction. incf eeadrl,f ; still loading latches increment address goto loop ; write next latches start_write bcf eecon1,lwlo ; no more loading latches - actually start flash program ; memory write movlw 55h ; start of required write sequence: movwf eecon2 ; write 55h movlw 0aah ; movwf eecon2 ; write aah bsf eecon1,wr ; set wr bit to begin write nop ; any instructions here are ignored as processor ; halts to begin write sequence nop ; processor will stop here and wait for write complete. ; after write processor continues with 3rd instruction bcf eecon1,wren ; disable writes bsf intcon,gie ; enable interrupts required sequence required sequence
? 2011-2012 microchip technology inc. ds41441c-page 95 pic12(l)f1840 11.4 modifying flash program memory when modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a ram image. program memory is modified using the following steps: 1. load the starting address of the row to be mod- ified. 2. read the existing data from the row into a ram image. 3. modify the ram image to contain the new data to be written into program memory. 4. load the starting address of the row to be rewrit- ten. 5. erase the program memory row. 6. load the write latches with data from the ram image. 7. initiate a programming operation. 8. repeat steps 6 and 7 as many times as required to reprogram the erased row. 11.5 user id, device id and configuration word access instead of accessing program memory or eeprom data memory, the user id?s, device id/revision id and configuration words can be accessed when cfgs = 1 in the eecon1 register. this is the region that would be pointed to by pc<15> = 1 , but not all addresses are accessible. different access may exist for reads and writes. refer to table 11-2 . when read access is initiated on an address outside the parameters listed in table 11-2 , the eedath:eedatl register pair is cleared. table 11-2: user id, device id and configuration word access (cfgs = 1 ) example 11-3: configuration word and device id access address function read access write access 8000h-8003h user ids yes yes 8006h device id/revision id yes no 8007h-8008h configuration words 1 and 2 yes no * this code block will read 1 word of program memory at the memory address: * prog_addr_lo (must be 00h-08h) data will be returned in the variables; * prog_data_hi, prog_data_lo banksel eeadrl ; select correct bank movlw prog_addr_lo ; movwf eeadrl ; store lsb of address clrf eeadrh ; clear msb of address bsf eecon1,cfgs ; select configuration space bcf intcon,gie ; disable interrupts bsf eecon1,rd ; initiate read nop ; executed (see figure 11-1 ) nop ; ignored (see figure 11-1 ) bsf intcon,gie ; restore interrupts movf eedatl,w ; get lsb of word movwf prog_data_lo ; store in user location movf eedath,w ; get msb of word movwf prog_data_hi ; store in user location
pic12(l)f1840 ds41441c-page 96 ? 2011-2012 microchip technology inc. 11.6 write verify depending on the application, good programming practice may dictate that the value written to the data eeprom or program memory should be verified (see example 11-6 ) to the desired value to be written. example 11-6 shows how to verify a write to eeprom. example 11-6: eeprom write verify banksel eedatl ; movf eedatl, w ;eedatl not changed ;from previous write bsf eecon1, rd ;yes, read the ;value written xorwf eedatl, w ; btfss status, z ;is data the same goto write_err ;no, handle error : ;yes, continue
? 2011-2012 microchip technology inc. ds41441c-page 97 pic12(l)f1840 11.7 register definitions: eeprom and flash control register 11-1: eedatl: eeprom data low byte register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u eedat<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 eedat<7:0> : read/write value for eeprom data byte or least significant bits of program memory register 11-2: eedath: eeprom data high byte register u-0 u-0 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u ? ? eedat<13:8> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 ? bit 5-0 eedat<13:8> : read/write value for most significant bits of program memory register 11-3: eeadrl: eeprom address register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 eeadr<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 eeadr<7:0> : specifies the least significant bits for program memory addre ss or eeprom address register 11-4: eeadrh: eeprom address high byte register u-1 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ? (1) eeadr<14:8> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 unimplemented: read as ? 1 ? bit 6-0 eeadr<14:8> : specifies the most significant bits for program memory address or eeprom address note 1: unimplemented, read as ? 1 ?.
pic12(l)f1840 ds41441c-page 98 ? 2011-2012 microchip technology inc. register 11-5: eecon1: eeprom control 1 register r/w-0/0 r/w-0/0 r/w-0/0 r/w/hc-0/0 r/w-x/q r/w-0/0 r/s/hc-0/0 r/s/hc-0/0 eepgd cfgs lwlo free wrerr wren wr rd bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? s = bit can only be set x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared hc = bit is cleared by hardware bit 7 eepgd: flash program/data eeprom memory select bit 1 = accesses program space flash memory 0 = accesses data eeprom memory bit 6 cfgs: flash program/data eeprom or configuration select bit 1 = accesses configuration, user id and device id registers 0 = accesses flash program or data eeprom memory bit 5 lwlo: load write latches only bit if cfgs = 1 (configuration space) or cfgs = 0 and eepgd = 1 (program flash) : 1 = the next wr command does not initiate a write; only the program memory latches are updated. 0 = the next wr command writes a value from eedath:eedatl into program memory latches and initiates a write of all the data stored in the program memory latches. if cfgs = 0 and eepgd = 0 : (accessing data eeprom) lwlo is ignored. the next wr command initiates a write to the data eeprom. bit 4 free: program flash erase enable bit if cfgs = 1 (configuration space) or cfgs = 0 and eepgd = 1 (program flash) : 1 = performs an erase operation on the next wr command (cleared by hardware after comple- tion of erase). 0 = performs a write operation on the next wr command. if eepgd = 0 and cfgs = 0 : (accessing data eeprom) free is ignored. the next wr command will initiate both a erase cycle and a write cycle. bit 3 wrerr: eeprom error flag bit 1 = condition indicates an improper program or erase sequence attempt or termination (bit is set automatically on any set attempt (write ? 1 ?) of the wr bit). 0 = the program or erase operation completed normally. bit 2 wren: program/erase enable bit 1 = allows program/erase cycles 0 = inhibits programming/erasing of program flash and data eeprom bit 1 wr: write control bit 1 = initiates a program flash or data eeprom program/erase operation. the operation is self-timed and the bit is cleared by hardware once operation is complete. the wr bit can only be set (not cleared) in software. 0 = program/erase operation to the flash or data eeprom is complete and inactive. bit 0 rd: read control bit 1 = initiates a program flash or data eeprom read. read takes one cycle. rd is cleared in hardware. the rd bit can only be set (not cleared) in software. 0 = does not initiate a program flash or data eeprom data read.
? 2011-2012 microchip technology inc. ds41441c-page 99 pic12(l)f1840 table 11-3: summary of registers associated with data eeprom register 11-6: eecon2: eeprom control 2 register w-0/0 w-0/0 w-0/0 w-0/0 w-0/0 w-0/0 w-0/0 w-0/0 eeprom control register 2 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? s = bit can only be set x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 data eeprom unlock pattern bits to unlock writes, a 55h must be written first, followed by an aah, before setting the wr bit of the eecon1 register. the value written to this register is used to unlock the writes. there are specific timing requirements on these writes. refer to section 11.2.2 ?writing to the data eeprom memory? for more information. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page eecon1 eepgd cfgs lwlo free wrerr wren wr rd 98 eecon2 eeprom control register 2 (not a physical register) 99 * eeadrl eeadrl<7:0> 97 eeadrh ? (1) eeadrh<6:0 97 eedatl eedatl<7:0> 97 eedath ? ? eedath<5:0> 97 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 74 pie2 osfie ? c1ie eeie bcl1ie ? ? ? 76 pir2 osfif ? c1if eeif bcl1if ? ? ? 78 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by data eeprom module. * page provides register information. note 1: unimplemented, read as ? 1 ?.
pic12(l)f1840 ds41441c-page 100 ? 2011-2012 microchip technology inc. notes:
? 2011-2012 microchip technology inc. ds41441c-page 101 pic12(l)f1840 12.0 i/o ports in general, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. the port has three registers for its operation. these registers are: ? trisa register (data direction register) ? porta register (reads the levels on the pins of the device) ? lata register (output latch) porta has the following additional registers. they are: ? ansela (analog select) ? wpua (weak pull-up) the data latch (lata register) is useful for read-modify-write operations on the value that the i/o pins are driving. a write operation to the lata register has the same affect as a write to the corresponding porta register. a read of the lata register reads of the values held in the i/o port latches, while a read of the porta register reads the actual i/o pin value. the port has analog functions and has an ansela. register which can disable the digital input and save power. a simplified model of a generic i/o port, without the interfaces to other peripherals, is shown in figure 12-1 . figure 12-1: generic i/o port operation 12.1 alternate pin function the alternate pin function control (apfcon) register is used to steer specific peripheral input and output functions between different pins. the apfcon register is shown in register 12-1 . for this device family, the following functions can be moved between different pins. ?rx/dt ?tx/ck ?sdo ?ss (slave select) ?t1g ?p1b ? ccp1/p1a these bits have no effect on the values of any tris register. port and tris overrides will be routed to the correct pin. the unselected pin will be unaffected. q d ck write latx data register i/o pin read portx write portx trisx read latx data bus to digital peripherals anselx v dd v ss to analog peripherals
pic12(l)f1840 ds41441c-page 102 ? 2011-2012 microchip technology inc. register 12-1: apfcon: alternate pin function co ntrol register r/w-0/0 r/w-0/0 r/w-0/0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 rxdtsel sdosel sssel ? t1gsel txcksel p1bsel ccp1sel bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 rxdtsel: pin selection bit 1 = rx/dt function is on ra5 0 = rx/dt function is on ra1 bit 6 sdosel: pin selection bit 1 = sdo function is on ra4 0 = sdo function is on ra0 bit 5 sssel: pin selection bit 1 =ss function is on ra0 0 =ss function is on ra3 bit 4 unimplemented: read as ? 0 ? bit 3 t1gsel: pin selection bit 1 = t1g function is on ra3 0 = t1g function is on ra4 bit 2 txcksel: pin selection bit 1 = tx/ck function is on ra4 0 = tx/ck function is on ra0 bit 1 p1bsel: pin selection bit 1 = p1b function is on ra4 0 = p1b function is on ra0 bit 0 ccp1sel: pin selection bit 1 = ccp1/p1a function is on ra5 0 = ccp1/p1a function is on ra2
? 2011-2012 microchip technology inc. ds41441c-page 103 pic12(l)f1840 12.2 porta registers 12.2.1 data register porta is a 6-bit wide, bidirectional port. the corresponding data direction register is trisa ( register 12-3 ). setting a trisa bit (= 1 ) will make the corresponding porta pin an input (i.e., disable the output driver). clearing a trisa bit (= 0 ) will make the corresponding porta pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). the exception is ra3, which is input only and its tris bit will always read as ? 1 ?. example 12-1 shows how to initialize porta. reading the porta register ( register 12-2 ) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch (lata). 12.2.2 direction control the trisa register ( register 12-3 ) controls the porta pin output drivers, even when they are being used as analog inputs. the user should ensure the bits in the trisa register are maintained set when using them as analog inputs. i/o pins configured as analog input always read ? 0 ?. 12.2.3 ansela register the ansela register ( register 12-5 ) is used to configure the input mode of an i/o pin to analog. setting the appropriate ansela bit high will cause all digital reads on the pin to be read as ? 0 ? and allow analog functions on the pin to operate correctly. the state of the ansela bits has no affect on digital output functions. a pin with tris clear and ansel set will still operate as a digital output, but the input mode will be analog. this can cause unexpected behavior when executing read-modify-write instructions on the affected port. example 12-1: initializing porta note: the ansela register must be initialized to configure an analog channel as a digital input. pins configured as analog inputs will read ? 0 ?. banksel porta ; clrf porta ;init porta banksel lata ;data latch clrf lata ; banksel ansela ; clrf ansela ;digital i/o banksel trisa ; movlw b'00111000' ;set ra<5:3> as inputs movwf trisa ;and set ra<2:0> as ;outputs
pic12(l)f1840 ds41441c-page 104 ? 2011-2012 microchip technology inc. 12.2.4 porta functions and output priorities each porta pin is multiplexed with other functions. the pins, their combined functions and their output priorities are shown in table 12-1 . when multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. analog input functions, such as adc, comparator and capsense inputs, are not shown in the priority lists. these inputs are active when the i/o pin is set for analog mode using the anselx registers. digital output functions may control the pin when it is in analog mode as shown in the priority list. table 12-1: porta output priority pin name function priority (1) ra0 icspdat icddat dacout mdout tx/ck (1) sdo (1) p1b (1) ra1 icspclk icdclk scl rx/dt (1) sck ra2 srq c1out sda ccp1/p1a (1) ra3 no output priorities. input only pin. ra4 osc2 clkout t1oso clkr tx/ck (1) sdo (1) p1b (1) ra5 osc1 t1osi srnq rx/dt (1) ccp1/p1a (1) note 1: priority listed from highest to lowest. 2: see apfcon register ( register 12-1 ).
? 2011-2012 microchip technology inc. ds41441c-page 105 pic12(l)f1840 12.3 register definitions: porta register 12-2: porta: porta register u-0 u-0 r/w-x/x r/w-x/x r-x/x r/w-x/x r/w-x/x r/w-x/x ? ? ra5 ra4 ra3 ra2 ra1 ra0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 bit 5-0 ra<5:0> : porta i/o value bits (1) 1 = port pin is > v ih 0 = port pin is < v il note 1: writes to porta are actually written to corresponding lata register. reads from porta register is return of actual i/o pin values. register 12-3: trisa: porta tri-state register u-0 u-0 r/w-1/1 r/w-1/1 r-1/1 r/w-1/1 r/w-1/1 r/w-1/1 ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 bit 5-4 trisa<5:4>: porta tri-state control bits 1 = porta pin configured as an input (tri-stated) 0 = porta pin configured as an output bit 3 trisa3: ra3 port tri-state control bit this bit is always ? 1 ? as ra3 is an input only bit 2-0 trisa<2:0>: porta tri-state control bits 1 = porta pin configured as an input (tri-stated) 0 = porta pin configured as an output
pic12(l)f1840 ds41441c-page 106 ? 2011-2012 microchip technology inc. register 12-4: lata: porta data latch register u-0 u-0 r/w-x/u r/w-x/u u-0 r/w-x/u r/w-x/u r/w-x/u ? ?lata5lata4 ? lata2 lata1 lata0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 bit 5-4 lata<5:4> : ra<5:4> output latch value bits (1) bit 3 unimplemented: read as ? 0 bit 2-0 lata<2:0> : ra<2:0> output latch value bits (1) note 1: writes to porta are actually written to corresponding lata register. reads from porta register is return of actual i/o pin values. register 12-5: ansela: porta analog select register u-0 u-0 u-0 r/w-1/1 u-0 r/w-1/1 r/w-1/1 r/w-1/1 ? ? ? ansa4 ? ansa2 ansa1 ansa0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-5 unimplemented: read as ? 0 ? bit 4 ansa4 : analog select between analog or digital function on pins ra4, respectively 1 = analog input. pin is assigned as analog input (1) . digital input buffer disabled. 0 = digital i/o. pin is assigned to port or digital special function. bit 3 unimplemented: read as ? 0 ? bit 2-0 ansa<2:0> : analog select between analog or digital function on pins ra<2:0>, respectively 1 = analog input. pin is assigned as analog input (1) . digital input buffer disabled. 0 = digital i/o. pin is assigned to port or digital special function. note 1: when setting a pin to an analog input, the corresponding tris bit must be set to input mode in order to allow external control of the voltage on the pin.
? 2011-2012 microchip technology inc. ds41441c-page 107 pic12(l)f1840 table 12-2: summary of regist ers associated with porta table 12-3: summary of conf iguration word with porta register 12-6: wpua: weak pull-up porta register u-0 u-0 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 ? ? wpua5 wpua4 wpua3 wpua2 wpua1 wpua0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 ? bit 5-0 wpua<5:0> : weak pull-up register bits 1 = pull-up enabled 0 = pull-up disabled note 1: global wpuen bit of the option_reg register must be cleared for individual pull-ups to be enabled. 2: the weak pull-up device is automatically disabled if the pin is in configured as an output. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ansela ? ? ?ansa4 ? ansa2 ansa1 ansa0 106 apfcon rxdtsel sdosel sssel --- t1gsel txcksel p1bsel ccp1sel 102 lata ? ?lata5lata4 ?lata2lata1lata0 106 option_reg wpuen intedg tmr0cs tmr0se psa ps<2:0> 151 porta ? ? ra5 ra4 ra3 ra2 ra1 ra0 105 trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 105 wpua ? ? wpua5 wpua4 wpua3 wpua2 wpua1 wpua0 107 legend: x = unknown, u = unchanged, ? = unimplemented locations read as ? 0 ?. shaded cells are not used by porta. name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config1 13:8 ? ? fcmen ieso clkouten boren<1:0> cpd 34 7:0 cp mclre pwrte wdte<1:0> fosc<2:0> legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by porta.
pic12(l)f1840 ds41441c-page 108 ? 2011-2012 microchip technology inc. notes:
? 2011-2012 microchip technology inc. ds41441c-page 109 pic12(l)f1840 13.0 interrupt-on-change the porta pins can be configured to operate as interrupt-on-change (ioc) pins. an interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. any individual porta pin, or combination of porta pins, can be configured to generate an interrupt. the interrupt-on-change module has the following features: ? interrupt-on-change enable (master switch) ? individual pin configuration ? rising and falling edge detection ? individual pin interrupt flags figure 13-1 is a block diagram of the ioc module. 13.1 enabling the module to allow individual porta pins to generate an interrupt, the iocie bit of the intcon register must be set. if the iocie bit is disabled, the edge detection on the pin will still occur, but an interrupt will not be generated. 13.2 individual pin configuration for each porta pin, a rising edge detector and a falling edge detector are present. to enable a pin to detect a rising edge, the associated iocapx bit of the iocap register is set. to enable a pin to detect a falling edge, the associated iocanx bit of the iocan register is set. a pin can be configured to detect rising and falling edges simultaneously by setting both the iocapx bit and the iocanx bit of the iocap and iocan registers, respectively. 13.3 interrupt flags the iocafx bits located in the iocaf register are status flags that correspond to the interrupt-on-change pins of porta. if an expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the iocie bit is set. the iocif bit of the intcon register reflects the status of all iocafx bits. 13.4 clearing interrupt flags the individual status flags, (iocafx bits), can be cleared by resetting them to zero. if another edge is detected during this clearing operation, the associated status flag will be set at the end of the sequence, regardless of the value actually being written. in order to ensure that no detected edge is lost while clearing flags, only and operations masking out known changed bits should be performed. the following sequence is an example of what should be performed. example 13-1: clearing interrupt flags (porta example) 13.5 operation in sleep the interrupt-on-change interrupt sequence will wake the device from sleep mode, if the iocie bit is set. if an edge is detected while in sleep mode, the iocaf register will be updated prior to the first instruction executed out of sleep. movlw 0xff xorwf iocaf, w andwf iocaf, f
pic12(l)f1840 ds41441c-page 110 ? 2011-2012 microchip technology inc. figure 13-1: interrupt-on -change block diagram d ck r q d ck r q rax iocanx iocapx q2 d ck s q q4q1 data bus = 0 or 1 write iocafx iocie to data bus iocafx edge detect ioc interrupt to cpu core from all other iocafx individual pin detectors q1 q2 q3 q4 q4q1 q1 q2 q3 q4 q1 q2 q3 q4 q4 q4q1 q4q1 q4q1
? 2011-2012 microchip technology inc. ds41441c-page 111 pic12(l)f1840 13.6 register definitions: interrupt-on-change control register 13-1: iocap: interrupt-on-c hange porta positive edge register u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ? ? iocap5 iocap4 iocap3 iocap2 iocap1 iocap0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 ? bit 5-0 iocap<5:0>: interrupt-on-change porta positive edge enable bits 1 = interrupt-on-change enabled on the pin for a positive going edge. associated status bit and interrupt flag will be set upon detecting an edge. 0 = interrupt-on-change disabled for the associated pin. register 13-2: iocan: interrupt-on-change porta negative edge register u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ? ? iocan5 iocan4 iocan3 iocan2 iocan1 iocan0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 ? bit 5-0 iocan<5:0>: interrupt-on-change porta negative edge enable bits 1 = interrupt-on-change enabled on the pin for a negative going edge. associated status bit and interrupt flag will be set upon detecting an edge. 0 = interrupt-on-change disabled for the associated pin. register 13-3: iocaf: interrupt- on-change porta flag register u-0 u-0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 ? ? iocaf5 iocaf4 iocaf3 iocaf2 iocaf1 iocaf0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared hs - bit is set in hardware bit 7-6 unimplemented: read as ? 0 ? bit 5-0 iocaf<5:0>: interrupt-on-change porta flag bits 1 = an enabled change was detected on the associated pin. set when iocapx = 1 and a rising edge was detected on rax, or when iocanx = 1 and a falling edge was detected on rax. 0 = no change was detected, or the user cleared the detected change.
pic12(l)f1840 ds41441c-page 112 ? 2011-2012 microchip technology inc. table 13-1: summary of registers as sociated with interrupt-on-change name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ansela ? ? ?ansa4 ? ansa2 ansa1 ansa0 106 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 74 iocaf ? ? iocaf5 iocaf4 iocaf3 iocaf2 iocaf1 iocaf0 111 iocan ? ? iocan5 iocan4 iocan3 iocan2 iocan1 iocan0 111 iocap ? ? iocap5 iocap4 iocap3 iocap2 iocap1 iocap0 111 trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 105 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by interrupt-on-change.
? 2011-2012 microchip technology inc. ds41441c-page 113 pic12(l)f1840 14.0 fixed voltage reference (fvr) the fixed voltage reference, or fvr, is a stable voltage reference, independent of v dd , with 1.024v, 2.048v or 4.096v selectable output levels. the output of the fvr can be configured to supply a reference voltage to the following: ? adc input channel ? adc positive reference ? comparator positive input ? digital-to-analog converter (dac) ? capacitive sensing (cps) module the fvr can be enabled by setting the fvren bit of the fvrcon register. 14.1 independent gain amplifiers the output of the fvr supplied to the adc, comparators, dac and cps module is routed through two independent programmable gain amplifiers. each amplifier can be programmed for a gain of 1x, 2x or 4x, to produce the three possible voltage levels. the adfvr<1:0> bits of the fvrcon register are used to enable and configure the gain amplifier settings for the reference supplied to the adc module. refer- ence section 16.0 ?analog-to-digital converter (adc) module? for additional information. the cdafvr<1:0> bits of the fvrcon register are used to enable and configure the gain amplifier settings for the reference supplied to the comparators, dac, and cps module. reference section 17.0 ?digital-to- analog converter (dac) module? , section 19.0 ?comparator module? and section 17.0 ?digital-to- analog converter (dac) module? for additional information. 14.2 fvr stabilization period when the fixed voltage reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. once the circuits stabilize and are ready for use, the fvrrdy bit of the fvrcon register will be set. see section 30.0 ?electrical specifications? for the minimum delay requirement. figure 14-1: voltage reference block diagram adfvr<1:0> cdafvr<1:0> x 1 x 2 x 4 x 1 x 2 x 4 2 2 fvr_buffer1 (to adc module) fvr_buffer2 (to comparators, dac, cps) + _ fvren fvrrdy any peripheral requiring the fixed reference (see figure 14-1 )
pic12(l)f1840 ds41441c-page 114 ? 2011-2012 microchip technology inc. table 14-1: peripherals requiring the fixed voltage reference (fvr) peripheral conditions description hfintosc fosc<2:0> = 100 and ircf<3:0> = 000x intosc is active and device is not in sleep. bor boren<1:0> = 11 bor always enabled. boren<1:0> = 10 and borfs = 1 bor disabled in sleep mode, bor fast start enabled. boren<1:0> = 01 and borfs = 1 bor under software control, bor fast start enabled. ldo all pic12f1840 devices, when vregpm = 1 and not in sleep the device runs off of the low-power regulator when in sleep mode.
? 2011-2012 microchip technology inc. ds41441c-page 115 pic12(l)f1840 14.3 register definitions: fvr control table 14-2: summary of registers associated with fixed voltage reference register 14-1: fvrcon: fixed voltage reference control register r/w-0/0 r-q/q r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 fvren fvrrdy (1) tsen tsrng cdafvr<1:0> adfvr<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared q = value depends on condition bit 7 fvren: fixed voltage reference enable bit 1 = fixed voltage reference is enabled 0 = fixed voltage reference is disabled bit 6 fvrrdy: fixed voltage reference ready flag bit (1) 1 = fixed voltage reference output is ready for use 0 = fixed voltage reference output is not ready or not enabled bit 5 tsen: temperature indicator enable bit (3) 1 = temperature indicator is enabled 0 = temperature indicator is disabled bit 4 tsrng: temperature indicator range selection bit 1 =v out = v dd - 4v t (high range) 0 =v out = v dd - 2v t (low range) bit 3-2 cdafvr<1:0>: comparator and dac fixed voltage reference selection bits 11 = comparator, dac and cps module fixed voltage reference peripheral output is 4x (4.096v) (2) 10 = comparator, dac and cps module fixed voltage reference peripheral output is 2x (2.048v) (2) 01 = comparator, dac and cps module fixed voltage reference peripheral output is 1x (1.024v) 00 = comparator, dac and cps module fixed voltage reference peripheral output is off bit 1-0 adfvr<1:0>: adc fixed voltage reference selection bits 11 = adc fixed voltage reference peripheral output is 4x (4.096v) (2) 10 = adc fixed voltage reference peripheral output is 2x (2.048v) (2) 01 = adc fixed voltage reference peripheral output is 1x (1.024v) 00 = adc fixed voltage reference peripheral output is off note 1: fvrrdy is always ? 1 ? on pic12f1840 only. 2: fixed voltage reference output cannot exceed v dd . 3: see section 15.0 ?temperature indicator module? for additional information. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page fvrcon fvren fvrrdy tsen tsrng cdafvr<1:0> adfvr<1:0> 115 legend: shaded cells are unused by the fixed voltage reference module.
pic12(l)f1840 ds41441c-page 116 ? 2011-2012 microchip technology inc. notes:
? 2011-2012 microchip technology inc. ds41441c-page 117 pic12(l)f1840 15.0 temperature indicator module this family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. the circuit's range of operating temperature falls between -40c and +85c. the output is a voltage that is proportional to the device temperature. the output of the temperature indicator is internally connected to the device adc. the circuit may be used as a temperature threshold detector or a more accurate temperature indicator, depending on the level of calibration performed. a one- point calibration allows the circuit to indicate a temperature closely surrounding that point. a two-point calibration allows the circuit to sense the entire range of temperature more accurately. reference application note an1333, ? use and calibration of the internal temperature indicator ? (ds01333) for more details regarding the calibration process. 15.1 circuit operation figure 15-1 shows a simplified block diagram of the temperature circuit. the proportional voltage output is achieved by measuring the forward voltage drop across multiple silicon junctions. equation 15-1 describes the output characteristics of the temperature indicator. equation 15-1: v out ranges the temperature sense circuit is integrated with the fixed voltage reference (fvr) module. see section 14.0 ?fixed voltage reference (fvr)? for more information. the circuit is enabled by setting the tsen bit of the fvrcon register. when disabled, the circuit draws no current. the circuit operates in either high or low range. the high range, selected by setting the tsrng bit of the fvrcon register, provides a wider output voltage. this provides more resolution over the temperature range, but may be less consistent from part to part. this range requires a higher bias voltage to operate and thus, a higher v dd is needed. the low range is selected by clearing the tsrng bit of the fvrcon register. the low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. the low range is provided for low voltage operation. figure 15-1: temperature circuit diagram 15.2 minimum operating v dd when the temperature circuit is operated in low range, the device may be operated at any operating voltage that is within specifications. when the temperature circuit is operated in high range, the device operating voltage, v dd , must be high enough to ensure that the temperature circuit is correctly biased. table 15-1 shows the recommended minimum v dd vs. range setting. table 15-1: recommended v dd vs. range 15.3 temperature output the output of the circuit is measured using the internal analog-to-digital converter. a channel is reserved for the temperature circuit output. refer to section 16.0 ?analog-to-digital converter (adc) module? for detailed information. high range: v out = v dd - 4v t low range: v out = v dd - 2v t min. v dd , tsrng = 1 min. v dd , tsrng = 0 3.6v 1.8v note: every time the adc mux is changed to the temperature indicator output selection (chs bit in the adccon0 register), wait 500 ? sec for the sampling capacitor to fully charge before sampling the temperature indicator output. tsen tsrng v dd v out to a d c
pic12(l)f1840 ds41441c-page 118 ? 2011-2012 microchip technology inc. 15.3.1 acquisition time to ensure accurate temperature measurements, the user must wait at least 200 ? s after the adc input multiplexer is connected to the temperature indicator output before the conversion is performed. in addition, the user must wait 200 ? s between sequential conver- sions of the temperature indicator output. table 15-2: summary of registers associated with the temperature indicator name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page fvrcon fvren fvrrdy tsen tsrng cdafvr<1:0> adfvr<1:0> 115 legend: shaded cells are unused by the temperature indicator module.
? 2011-2012 microchip technology inc. ds41441c-page 119 pic12(l)f1840 16.0 analog-to-digital converter (adc) module the analog-to-digital converter (adc) allows conversion of an analog input signal to a 10-bit binary representation of that signal. this device uses analog inputs, which are multiplexed into a single sample and hold circuit. the output of the sample and hold is connected to the input of the converter. the converter generates a 10-bit binary result via successive approximation and stores the conversion result into the adc result registers (adresh:adresl register pair). figure 16-1 shows the block diagram of the adc. the adc voltage reference is software selectable to be either internally generated or externally supplied. the adc can generate an interrupt upon completion of a conversion. this interrupt can be used to wake-up the device from sleep. figure 16-1: adc block diagram note 1: when adon = 0 , all multiplexer inputs are disconnected. dac_output v dd v ref adpref = 10 adpref = 00 adpref = 11 fvr buffer1 adon (1) go/done v ss adc 00000 00001 00010 00011 11110 chs<4:0> an0 an1 an2 an3 11111 adresh adresl 10 16 adfm 0 = left justify 1 = right justify temp indicator 11101 ref+ ref-
pic12(l)f1840 ds41441c-page 120 ? 2011-2012 microchip technology inc. 16.1 adc configuration when configuring and using the adc the following functions must be considered: ? port configuration ? channel selection ? adc voltage reference selection ? adc conversion clock source ? interrupt control ? result formatting 16.1.1 port configuration the adc can be used to convert both analog and digital signals. when converting analog signals, the i/o pin should be configured for analog by setting the associated tris and ansel bits. refer to section 12.0 ?i/o ports? for more information. 16.1.2 channel selection there are seven channel selections available: ? an<3:0> pins ? temperature indicator ? dac_output ? fvr (fixed voltage reference) output refer to section 17.0 ?digital-to-analog converter (dac) module? , section 14.0 ?fixed voltage refer- ence (fvr)? and section 15.0 ?temperature indica- tor module? for more information on these channel selections. the chs bits of the adcon0 register determine which channel is connected to the sample and hold circuit. when changing channels, a delay is required before starting the next conversion. refer to section 16.2 ?adc operation? for more information. 16.1.3 adc voltage reference the adpref bits of the adcon1 register provides control of the positive voltage reference. the positive voltage reference can be: ?v ref + pin ?v dd see section 14.0 ?fixed voltage reference (fvr)? for more details on the fixed voltage reference. 16.1.4 conversion clock the source of the conversion clock is software select- able via the adcs bits of the adcon1 register. there are seven possible clock options: ?f osc /2 ?f osc /4 ?f osc /8 ?f osc /16 ?f osc /32 ?f osc /64 ?f rc (dedicated internal f rc oscillator) the time to complete one bit conversion is defined as t ad . one full 10-bit conversion requires 11.5 t ad periods as shown in figure 16-2 . for correct conversion, the appropriate t ad specifica- tion must be met. refer to the adc conversion require- ments in section 30.0 ?electrical specifications? for more information. table 16-1 gives examples of appropriate adc clock selections. note: analog voltages on any pin that is defined as a digital input may cause the input buf- fer to conduct excess current. note: unless using the f rc , any changes in the system clock frequency will change the adc clock frequency, which may adversely affect the adc result.
? 2011-2012 microchip technology inc. ds41441c-page 121 pic12(l)f1840 table 16-1: adc clock period (t ad ) v s . device operating frequencies figure 16-2: analog-to-dig ital conversion t ad cycles adc clock period (t ad ) device frequency (f osc ) adc clock source adcs<2:0> 32 mhz 20 mhz 16 mhz 8 mhz 4 mhz 1 mhz fosc/2 000 62.5ns (2) 100 ns (2) 125 ns (2) 250 ns (2) 500 ns (2) 2.0 ? s fosc/4 100 125 ns (2) 200 ns (2) 250 ns (2) 500 ns (2) 1.0 ? s4.0 ? s fosc/8 001 0.5 ? s (2) 400 ns (2) 0.5 ? s (2) 1.0 ? s2.0 ? s 8.0 ? s (3) fosc/16 101 800 ns 800 ns 1.0 ? s2.0 ? s4.0 ? s 16.0 ? s (3) fosc/32 010 1.0 ? s1.6 ? s2.0 ? s4.0 ? s 8.0 ? s (3) 32.0 ? s (3) fosc/64 110 2.0 ? s3.2 ? s4.0 ? s 8.0 ? s (3) 16.0 ? s (3) 64.0 ? s (3) f rc x11 1.0-6.0 ? s (1,4) 1.0-6.0 ? s (1,4) 1.0-6.0 ? s (1,4) 1.0-6.0 ? s (1,4) 1.0-6.0 ? s (1,4) 1.0-6.0 ? s (1,4) legend: shaded cells are outside of recommended range. note 1: the f rc source has a typical t ad time of 1.6 ? s for v dd . 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. 4: the adc clock period (t ad ) and total adc conversion time can be minimized when the adc clock is derived from the system clock f osc . however, the f rc oscillator source must be used when conversions are to be performed with the device in sleep mode. t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 11 set go bit holding capacitor is disconnected from analog input (typically 100 ns) t ad 9 t ad 10 t cy - t ad adresh:adresl is loaded, go bit is cleared, adif bit is set, holding capacitor is connected to analog input. conversion starts b0 b9 b6 b5 b4 b3 b2 b1 b8 b7 on the following cycle:
pic12(l)f1840 ds41441c-page 122 ? 2011-2012 microchip technology inc. 16.1.5 interrupts the adc module allows for the ability to generate an interrupt upon completion of an analog-to-digital conversion. the adc interrupt flag is the adif bit in the pir1 register. the adc interrupt enable is the adie bit in the pie1 register. the adif bit must be cleared in software. this interrupt can be generated while the device is operating or while in sleep. if the device is in sleep, the interrupt will wake-up the device. upon waking from sleep, the next instruction following the sleep instruc- tion is always executed. if the user is attempting to wake-up from sleep and resume in-line code execu- tion, the gie and peie bits of the intcon register must be disabled. if the gie and peie bits of the intcon register are enabled, execution will switch to the interrupt service routine. 16.1.6 result formatting the 10-bit adc conversion result can be supplied in two formats, left justified or right justified. the adfm bit of the adcon1 register controls the output format. figure 16-3 shows the two output formats. figure 16-3: 10-bit adc conversion result format note 1: the adif bit is set at the completion of every conversion, regardless of whether or not the adc interrupt is enabled. 2: the adc operates during sleep only when the f rc oscillator is selected. adresh adresl (adfm = 0 )msb lsb bit 7 bit 0 bit 7 bit 0 10-bit adc result unimplemented: read as ? 0 ? (adfm = 1 ) msb lsb bit 7 bit 0 bit 7 bit 0 unimplemented: read as ? 0 ? 10-bit adc result
? 2011-2012 microchip technology inc. ds41441c-page 123 pic12(l)f1840 16.2 adc operation 16.2.1 starting a conversion to enable the adc module, the adon bit of the adcon0 register must be set to a ? 1 ?. setting the go/ done bit of the adcon0 register to a ? 1 ? will start the analog-to-digital conversion. 16.2.2 completion of a conversion when the conversion is complete, the adc module will: ? clear the go/done bit ? set the adif interrupt flag bit ? update the adresh and adresl registers with new conversion result 16.2.3 terminating a conversion if a conversion must be terminated before completion, the go/done bit can be cleared in software. the adresh and adresl registers will be updated with the partially complete analog-to-digital conversion sample. incomplete bits will match the last bit converted. 16.2.4 adc operation during sleep the adc module can operate during sleep. this requires the adc clock source to be set to the f rc option. when the f rc oscillator source is selected, the adc waits one additional instruction before starting the conversion. this allows the sleep instruction to be executed, which can reduce system noise during the conversion. if the adc interrupt is enabled, the device will wake-up from sleep when the conversion completes. if the adc interrupt is disabled, the adc module is turned off after the conversion completes, although the adon bit remains set. when the adc clock source is something other than f rc , a sleep instruction causes the present conver- sion to be aborted and the adc module is turned off, although the adon bit remains set. 16.2.5 special event trigger the special event trigger of the ccpx/eccpx module allows periodic adc measurements without software intervention. when this trigger occurs, the go/done bit is set by hardware and the timer1 counter resets to zero. using the special event trigger does not assure proper adc timing. it is the user?s responsibility to ensure that the adc timing requirements are met. refer to section 24.0 ?capture/compare/pwm modules? for more information. note: the go/done bit should not be set in the same instruction that turns on the adc. refer to section 16.2.6 ?adc conver- sion procedure? . note: a device reset forces all registers to their reset state. thus, the adc module is turned off and any pending conversion is terminated. table 16-2: special event trigger device eccp1 pic12f/lf1840 eccp1
pic12(l)f1840 ds41441c-page 124 ? 2011-2012 microchip technology inc. 16.2.6 adc conversion procedure this is an example procedure for using the adc to perform an analog-to-digital conversion: 1. configure port: ? disable pin output driver (refer to the tris register) ? configure pin as analog (refer to the ansel register) 2. configure the adc module: ? select adc conversion clock ? configure voltage reference ? select adc input channel ? turn on adc module 3. configure adc interrupt (optional): ? clear adc interrupt flag ? enable adc interrupt ? enable peripheral interrupt ? enable global interrupt (1) 4. wait the required acquisition time (2) . 5. start conversion by setting the go/done bit. 6. wait for adc conversion to complete by one of the following: ? polling the go/done bit ? waiting for the adc interrupt (interrupts enabled) 7. read adc result. 8. clear the adc interrupt flag (required if interrupt is enabled). example 16-1: adc conversion note 1: the global interrupt can be disabled if the user is attempting to wake-up from sleep and resume in-line code execution. 2: refer to section 16.4 ?adc acquisi- tion requirements? . ;this code block configures the adc ;for polling, vdd and vss references, frc ;clock and an0 input. ; ;conversion start & polling for completion ; are included. ; banksel adcon1 ; movlw b?11110000? ;right justify, frc ;clock movwf adcon1 ;vdd and vss vref banksel trisa ; bsf trisa,0 ;set ra0 to input banksel ansel ; bsf ansel,0 ;set ra0 to analog banksel adcon0 ; movlw b?00000001? ;select channel an0 movwf adcon0 ;turn adc on call sampletime ;acquisiton delay bsf adcon0,adgo ;start conversion btfsc adcon0,adgo ;is conversion done? goto $-1 ;no, test again banksel adresh ; movf adresh,w ;read upper 2 bits movwf resulthi ;store in gpr space banksel adresl ; movf adresl,w ;read lower 8 bits movwf resultlo ;store in gpr space
? 2011-2012 microchip technology inc. ds41441c-page 125 pic12(l)f1840 16.3 register definitions: adc control register 16-1: adcon0: ad c control register 0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ? chs<4:0> go/done adon bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 unimplemented: read as ? 0 ? bit 6-2 chs<4:0>: analog channel select bits 11111 = fvr (fixed voltage reference) buffer 1 output (2) 11110 = dac_output (1) 11101 = temperature indicator (3) . 11100 = reserved. no channel connected. ? ? ? 00100 = reserved. no channel connected. 00011 =an3 00010 =an2 00001 =an1 00000 =an0 bit 1 go/done : adc conversion status bit 1 = adc conversion cycle in progress. setting this bit starts an adc conversion cycle. this bit is automatically cleared by hardware when the adc conversion has completed. 0 = adc conversion completed/not in progress bit 0 adon: adc enable bit 1 = adc is enabled 0 = adc is disabled and consumes no operating current note 1: see section 17.0 ?digital-to-analog converter (dac) module? for more information. 2: see section 14.0 ?fixed voltage reference (fvr)? for more information. 3: see section 15.0 ?temperature indicator module? for more information.
pic12(l)f1840 ds41441c-page 126 ? 2011-2012 microchip technology inc. register 16-2: adcon1: ad c control register 1 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 u-0 r/w-0/0 r/w-0/0 adfm adcs<2:0> ? ? adpref<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 adfm: adc result format select bit 1 = right justified. six most significant bits of adresh are set to ? 0 ? when the conversion result is loaded. 0 = left justified. six least significant bits of adresl are set to ? 0 ? when the conversion result is loaded. bit 6-4 adcs<2:0>: adc conversion clock select bits 111 =f rc (clock supplied from a dedicated rc oscillator) 110 =f osc /64 101 =f osc /16 100 =f osc /4 011 =f rc (clock supplied from a dedicated rc oscillator) 010 =f osc /32 001 =f osc /8 000 =f osc /2 bit 3-2 unimplemented: read as ? 0 ? bit 1-0 adpref<1:0>: adc positive voltage reference configuration bits 11 =v ref is connected to internal fixed voltage reference (fvr) module (1) 10 =v ref is connected to external v ref pin (1) 01 = reserved 00 =v ref is connected to v dd note 1: when selecting the fvr or the v ref + pin as the source of the positive reference, be aware that a minimum voltage specification exists. see section 30.0 ?electrical specifications? for details.
? 2011-2012 microchip technology inc. ds41441c-page 127 pic12(l)f1840 register 16-3: adresh: adc result register high (adresh) adfm = 0 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u adres<9:2> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 adres<9:2> : adc result register bits upper 8 bits of 10-bit conversion result register 16-4: adresl: adc result register low (adresl) adfm = 0 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u adres<1:0> ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 adres<1:0> : adc result register bits lower 2 bits of 10-bit conversion result bit 5-0 reserved : do not use.
pic12(l)f1840 ds41441c-page 128 ? 2011-2012 microchip technology inc. register 16-5: adresh: adc result register high (adresh) adfm = 1 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u ? ? ? ? ? ? adres<9:8> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-2 reserved : do not use. bit 1-0 adres<9:8> : adc result register bits upper 2 bits of 10-bit conversion result register 16-6: adresl: adc result register low (adresl) adfm = 1 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u adres<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 adres<7:0> : adc result register bits lower 8 bits of 10-bit conversion result
? 2011-2012 microchip technology inc. ds41441c-page 129 pic12(l)f1840 16.4 adc acquisition requirements for the adc to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 16-4 . the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ), refer to figure 16-4 . the maximum recommended impedance for analog sources is 10 k ? . as the source impedance is decreased, the acquisition time may be decreased. after the analog input channel is selected (or changed), an adc acquisition must be done before the conversion can be started. to calculate the minimum acquisition time, equation 16-1 may be used. this equation assumes that 1/2 lsb error is used (1,024 steps for the adc). the 1/2 lsb error is the maximum error allowed for the adc to meet its specified resolution. equation 16-1: acquisition time example t acq amplifier settling time hold capacitor charging time temperature coefficient ++ = t amp t c t coff ++ = 2s t c temperature - 25c ?? 0.05s/c ?? ?? ++ = t c c hold r ic r ss r s ++ ?? ln(1/511) ? = 10pf 1k ? 7k ? 10k ? ++ ?? ? ln(0.001957) = 1.12 = s v applied 1e tc ? rc --------- ? ?? ?? ?? v applied 1 1 2 n1 + ?? 1 ? -------------------------- ? ?? ?? = v applied 1 1 2 n1 + ?? 1 ? -------------------------- ? ?? ?? v chold = v applied 1e t c ? rc --------- - ? ?? ?? ?? v chold = ;[1] v chold charged to within 1/2 lsb ;[2] v chold charge response to v applied ;combining [1] and [2] the value for t c can be approximated with the following equations: solving for t c : therefore: temperature 50c and external impedance of 10k ? 5.0v v dd = assumptions: note: where n = number of bits of the adc. t acq 2s 1.12s 50c- 25c ?? 0.05 s/c ?? ?? ++ = 4.42s = note 1: the reference voltage (v ref ) has no effect on the equation, since it cancels itself out. 2: the charge holding capacitor (c hold ) is not discharged after each conversion. 3: the maximum recommended impedance for analog sources is 10 k ? . this is required to meet the pin leakage specification.
pic12(l)f1840 ds41441c-page 130 ? 2011-2012 microchip technology inc. figure 16-4: analog input model figure 16-5: adc transfer function c pin va rs analog 5 pf v dd v t ? 0.6v v t ? 0.6v i leakage (1) r ic ? 1k sampling switch ss rss c hold = 10 pf v ss /v ref - 6v sampling switch 5v 4v 3v 2v 567891011 (k ? ) v dd legend: c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance various junctions r ss note 1: refer to section 30.0 ?electrical specifications? . r ss = resistance of sampling switch input pin 3ffh 3feh adc output code 3fdh 3fch 03h 02h 01h 00h full-scale 3fbh 0.5 lsb v ref - zero-scale transition v ref + transition 1.5 lsb full-scale range analog input voltage
? 2011-2012 microchip technology inc. ds41441c-page 131 pic12(l)f1840 table 16-3: summary of registers associated with adc name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page adcon0 ? chs<4:0> go/done adon 125 adcon1 adfm adcs<2:0> ? ? adpref<1:0> 126 adresh adc result register high 127 , 128 adresl adc result register low 127 , 128 ansela ? ? ?ansa4 ? ansa2 ansa1 ansa0 106 ccp1con p1m<1:0> dc1b<1:0> ccp1m<3:0> 197 daccon0 dacen daclps dacoe ? dacpss<1:0> ? ? 136 daccon1 ? ? ? dacr<4:0> 136 fvrcon fvren fvrrdy tsen tsrng cdafvr<1:0> adfvr<1:0> 115 intcon gie peie tmr0ie inte ioce tmr0if intf iocf 74 pie1 tmr1gie adie rcie txie ssp1ie ccp1ie tmr2ie tmr1ie 75 pir1 tmr1gif adif rcif txif ssp1if ccp1if tmr2if tmr1if 77 trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 105 legend: ? = unimplemented read as ? 0 ?. shaded cells are not used for adc module.
pic12(l)f1840 ds41441c-page 132 ? 2011-2012 microchip technology inc. notes:
? 2011-2012 microchip technology inc. ds41441c-page 133 pic12(l)f1840 17.0 digital-to-analog converter (dac) module the digital-to-analog converter supplies a variable voltage reference, ratiometric with the input source, with 32 selectable output levels. the input of the dac can be connected to: ?external v ref pins ?v dd supply voltage ? fvr (fixed voltage reference) the output of the dac can be configured to supply a reference voltage to the following: ? comparator positive input ? adc input channel ?dacout pin ? capacitive sensing (cps) module the digital-to-analog converter (dac) can be enabled by setting the dacen bit of the daccon0 register. 17.1 output voltage selection the dac has 32 voltage level ranges. the 32 levels are set with the dacr<4:0> bits of the daccon1 register. the dac output voltage is determined by the following equations: equation 17-1: dac output voltage 17.2 ratiometric output level the dac output value is derived using a resistor ladder with each end of the ladder tied to a positive and negative voltage reference input source. if the voltage of either input source fluctuates, a similar fluctuation will result in the dac output value. the value of the individual resistors within the ladder can be found in section 30.0 ?electrical specifications? . 17.3 dac voltage reference output the dac can be output to the dacout pin by setting the dacoe bit of the daccon0 register to ? 1 ?. selecting the dac reference voltage for output on the dacout pin automatically overrides the digital output buffer and digital input threshold detector functions of that pin. reading the dacout pin when it has been configured for dac reference voltage output will always return a ? 0 ?. due to the limited current drive capability, a buffer must be used on the dac voltage reference output for external connections to dacout. figure 17-2 shows an example buffering technique. if dacen = 1 if dacen = 0 & daclps = 1 & dacr[4:0] = 11111 v out v source + = if dacen = 0 & daclps = 0 & dacr[4:0] = 00000 v out v source ? = v source + = v dd , v ref , or fvr buffer 2 v source - = v ss v out v source +v source - ? ?? dacr 4:0 ?? 2 5 ----------------------------- ? ?? ?? v source - + =
pic12(l)f1840 ds41441c-page 134 ? 2011-2012 microchip technology inc. figure 17-1: digital-to-analog co nverter block diagram figure 17-2: voltage reference ou tput buffer example 32-to-1 mux dacr<4:0> r r r r r r r 32 dac_output dacout 5 (to comparator, cps and adc modules) dacoe v dd v ref dacpss<1:0> 2 dacen steps digital-to-analog converter (dac) fvr buffer2 r v source - v source + v ss daclps dacout buffered dac output + ? dac module voltage reference output impedance r pic ? mcu
? 2011-2012 microchip technology inc. ds41441c-page 135 pic12(l)f1840 17.4 low-power voltage state in order for the dac module to consume the least amount of power, one of the two voltage reference input sources to the resistor ladder must be disconnected. either the positive voltage source, (v source +), or the negative voltage source, (v source -) can be disabled. the negative voltage source is disabled by setting the daclps bit in the daccon0 register. clearing the daclps bit in the daccon0 register disables the positive voltage source. 17.4.1 output clamped to positive voltage source the dac output voltage can be set to v source + with the least amount of power consumption by performing the following: ? clearing the dacen bit in the daccon0 register. ? setting the daclps bit in the daccon0 register. ? configuring the dacpss bits to the proper positive source. ? configuring the dacr<4:0> bits to ? 11111 ? in the daccon1 register. this is also the method used to output the voltage level from the fvr to an output pin. see section 17.5 ?operation during sleep? for more information. reference figure 17-3 for output clamping examples. 17.4.2 output clamped to negative voltage source the dac output voltage can be set to v source - with the least amount of power consumption by performing the following: ? clearing the dacen bit in the daccon0 register. ? clearing the daclps bit in the daccon0 register. ? configuring the dacr<4:0> bits to ? 00000 ? in the daccon1 register. this allows the comparator to detect a zero-crossing while not consuming additional current through the dac module. reference figure 17-3 for output clamping examples. figure 17-3: output volt age clamping examples 17.5 operation during sleep when the device wakes up from sleep through an interrupt or a watchdog timer time-out, the contents of the daccon0 register are not affected. to minimize current consumption in sleep mode, the voltage reference should be disabled. 17.6 effects of a reset a device reset affects the following: ? dac is disabled. ? dac output voltage is removed from the dacout pin. ? the dacr<4:0> range select bits are cleared. r r r dac voltage ladder (see figure 17-1 ) v source + dacen = 0 daclps = 1 dacr<4:0> = 11111 v source - r r r dac voltage ladder (see figure 17-1 ) v source + dacen = 0 daclps = 0 dacr<4:0> = 00000 v source - output clamped to positive voltage source output clamped to negative voltage source
pic12(l)f1840 ds41441c-page 136 ? 2011-2012 microchip technology inc. 17.7 register definitions: dac control table 17-1: summary of registers asso ciated with the dac module register 17-1: daccon0: voltage re ference control register 0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 r/w-0/0 r/w-0/0 u-0 u-0 dacen daclps dacoe ? dacpss<1:0> ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 dacen: dac enable bit 1 = dac is enabled 0 = dac is disabled bit 6 daclps: dac low-power voltage state select bit 1 = dac positive reference source selected 0 = dac negative reference source selected bit 5 dacoe: dac voltage output enable bit 1 = dac voltage level is also an output on the dacout pin 0 = dac voltage level is disconnected from the dacout pin bit 4 unimplemented: read as ? 0 ? bit 3-2 dacpss<1:0>: dac positive source select bits 11 = reserved, do not use 10 = fvr buffer2 output 01 =v ref pin 00 =v dd bit 1-0 unimplemented: read as ? 0 ? register 17-2: daccon1: voltage re ference control register 1 u-0 u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ? ? ? dacr<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-5 unimplemented: read as ? 0 ? bit 4-0 dacr<4:0>: dac voltage output select bits name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page fvrcon fvren fvrrdy tsen tsrng cdafvr<1:0> adfvr<1:0> 115 daccon0 dacen daclps dacoe ? dacpss<1:0> ? ? 136 daccon1 ? ? ? dacr<4:0> 136 legend: ? = unimplemented, read as ? 0 ?. shaded cells are unused by the dac module.
? 2011-2012 microchip technology inc. ds41441c-page 137 pic12(l)f1840 18.0 sr latch the module consists of a single sr latch with multiple set and reset inputs as well as separate latch outputs. the sr latch module includes the following features: ? programmable input selection ? sr latch output is available externally ? separate q and q outputs ? firmware set and reset the sr latch can be used in a variety of analog appli- cations, including oscillator circuits, one-shot circuit, hysteretic controllers, and analog timing applications. 18.1 latch operation the latch is a set-reset latch that does not depend on a clock source. each of the set and reset inputs are active-high. the latch can be set or reset by: ? software control (srps and srpr bits) ? comparator c1 output (sync_c1out) ?sri pin ? programmable clock (srclk) the srps and the srpr bits of the srcon0 register may be used to set or reset the sr latch, respectively. the latch is reset-dominant. therefore, if both set and reset inputs are high, the latch will go to the reset state. both the srps and srpr bits are self resetting which means that a single write to either of the bits is all that is necessary to complete a latch set or reset operation. the output from comparator c1 can be used as the set or reset inputs of the sr latch. the output of the comparator can be synchronized to the timer1 clock source. see section 19.0 ?comparator module? and section 21.0 ?timer1 module with gate control? for more information. an external source on the sri pin can be used as the set or reset inputs of the sr latch. an internal clock source is available that can periodically set or reset the sr latch. the srclk<2:0> bits in the srcon0 register are used to select the clock source period. the srscke and srrcke bits of the srcon1 register enable the clock source to set or reset the sr latch, respectively. 18.2 latch output the srqen and srnqen bits of the srcon0 regis- ter control the q and q latch outputs. both of the sr latch outputs may be directly output to an i/o pin at the same time. the applicable tris bit of the corresponding port must be cleared to enable the port pin output driver. 18.3 effects of a reset upon any device reset, the sr latch output is not ini- tialized to a known state. the user?s firmware is responsible for initializing the latch output before enabling the output pins.
pic12(l)f1840 ds41441c-page 138 ? 2011-2012 microchip technology inc. figure 18-1: sr latch simplified block diagram table 18-1: srclk frequency table srps s r q q note 1: if r = 1 and s = 1 simultaneously, q = 0 , q = 1 2: pulse generator causes a 1 q-state pulse width. 3: name denotes the connection point at the comparator output. pulse gen ( 2 ) sr latch (1) srqen srspe srscke srclk srsc1e sync_c1out (3) srpr pulse gen ( 2 ) srrpe srrcke srclk srrc1e sync_c1out (3) srlen srnqen srlen srq srnq sri sri srclk divider f osc = 32 mhz f osc = 20 mhz f osc = 16 mhz f osc = 4 mhz f osc = 1 mhz 111 512 62.5 khz 39.0 khz 31.3 khz 7.81 khz 1.95 khz 110 256 125 khz 78.1 khz 62.5 khz 15.6 khz 3.90 khz 101 128 250 khz 156 khz 125 khz 31.25 khz 7.81 khz 100 64 500 khz 313 khz 250 khz 62.5 khz 15.6 khz 011 32 1 mhz 625 khz 500 khz 125 khz 31.3 khz 010 16 2 mhz 1.25 mhz 1 mhz 250 khz 62.5 khz 001 8 4 mhz 2.5 mhz 2 mhz 500 khz 125 khz 000 4 8 mhz 5 mhz 4 mhz 1 mhz 250 khz
? 2011-2012 microchip technology inc. ds41441c-page 139 pic12(l)f1840 18.4 register definitions: sr latch control register 18-1: srcon0: sr latch control 0 register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/s-0/0 r/s-0/0 srlen srclk<2:0> srqen srnqen srps srpr bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared s = bit is set only bit 7 srlen: sr latch enable bit 1 = sr latch is enabled 0 = sr latch is disabled bit 6-4 srclk<2:0>: sr latch clock divider bits 111 = generates a 1 f osc wide pulse every 512th f osc cycle clock 110 = generates a 1 f osc wide pulse every 256th f osc cycle clock 101 = generates a 1 f osc wide pulse every 128th f osc cycle clock 100 = generates a 1 f osc wide pulse every 64th f osc cycle clock 011 = generates a 1 f osc wide pulse every 32nd f osc cycle clock 010 = generates a 1 f osc wide pulse every 16th f osc cycle clock 001 = generates a 1 f osc wide pulse every 8th f osc cycle clock 000 = generates a 1 f osc wide pulse every 4th f osc cycle clock bit 3 srqen: sr latch q output enable bit if srlen = 1 : 1 = q is present on the srq pin 0 = external q output is disabled if srlen = 0 : sr latch is disabled bit 2 srnqen: sr latch q output enable bit if srlen = 1 : 1 =q is present on the srnq pin 0 = external q output is disabled if srlen = 0 : sr latch is disabled bit 1 srps: pulse set input of the sr latch bit (1) 1 = pulse set input for 1 q-clock period 0 = no effect on set input. bit 0 srpr: pulse reset input of the sr latch bit (1) 1 = pulse reset input for 1 q-clock period 0 = no effect on reset input. note 1: set only, always reads back ? 0 ?.
pic12(l)f1840 ds41441c-page 140 ? 2011-2012 microchip technology inc. table 18-2: summary of registers as sociated with sr latch module register 18-2: srcon1: sr latch control 1 register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 srspe srscke reserved srsc1e srrpe srrcke reserved srrc1e bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 srspe: sr latch peripheral set enable bit 1 = sr latch is set when the sri pin is high 0 = sri pin has no effect on the set input of the sr latch bit 6 srscke: sr latch set clock enable bit 1 = set input of sr latch is pulsed with srclk 0 = srclk has no effect on the set input of the sr latch bit 5 reserved: read as ? 0 ?. maintain this bit clear. bit 4 srsc1e: sr latch c1 set enable bit 1 = sr latch is set when the c1 comparator output is high 0 = c1 comparator output has no effect on the set input of the sr latch bit 3 srrpe: sr latch peripheral reset enable bit 1 = sr latch is reset when the sri pin is high 0 = sri pin has no effect on the reset input of the sr latch bit 2 srrcke: sr latch reset clock enable bit 1 = reset input of sr latch is pulsed with srclk 0 = srclk has no effect on the reset input of the sr latch bit 1 reserved: read as ? 0 ?. maintain this bit clear. bit 0 srrc1e: sr latch c1 reset enable bit 1 = sr latch is reset when the c1 comparator output is high 0 = c1 comparator output has no effect on the reset input of the sr latch name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page srcon0 srlen srclk<2:0> srqen srnqen srps srpr 139 srcon1 srspe srscke reserved srsc1e srrpe srrcke reserved srrc1e 140 trisa ? ?trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 105 legend: ? = unimplemented, read as ? 0 ?. shaded cells are unused by the sr latch module.
? 2011-2012 microchip technology inc. ds41441c-page 141 pic12(l)f1840 19.0 comparator module comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. comparators are very useful mixed signal building blocks because they provide analog functionality independent of program execution. the analog comparator module includes the following features: ? independent comparator control ? programmable input selection ? comparator output is available internally/externally ? programmable output polarity ? interrupt-on-change ? wake-up from sleep ? programmable speed/power optimization ?pwm shutdown ? programmable and fixed voltage reference 19.1 comparator overview a single comparator is shown in figure 19-1 along with the relationship between the analog input levels and the digital output. when the analog voltage at v in + is less than the analog voltage at v in -, the output of the comparator is a digital low level. when the analog voltage at v in + is greater than the analog voltage at v in -, the output of the comparator is a digital high level. the comparators available for this device are located in table 19-1 . figure 19-1: single comparator table 19-1: comparator availability per device device c1 pic12(l)f1840 ? + v in + v in - output output v in + v in - note: the black areas of the output of the comparator represents the uncertainty due to input offsets and response time.
pic12(l)f1840 ds41441c-page 142 ? 2011-2012 microchip technology inc. figure 19-2: comparator 1 module simplified block diagram note 1: when c1on = 0 , the comparator will produce a ? 0 ? at the output. 2: when c1on = 0 , all multiplexer inputs are disconnected. 3: output of comparator can be frozen during debugging. mux c1 (3) 0 1 c1on (1) c1nch 2 0 1 c1pch<1:0> c1in1- c1in+ mux - + c1vn c1vp c1out to eccp pwm logic q1 d en q c1pol mc1out set c1if 0 1 c1sync c1oe c1out dq sync_c1out dac fvr buffer2 c1in0- 2 c1sp c1hys det interrupt det interrupt c1intn c1intp to d a ta b u s 2 3 tris bit c1on (2) (2) (from timer1) t1clk to timer1 or sr latch v ss
? 2011-2012 microchip technology inc. ds41441c-page 143 pic12(l)f1840 19.2 comparator control the comparator has 2 control registers: cm1con0 and cm1con1. the cm1con0 register (see register 19-1 ) contains control and status bits for the following: ? enable ?output selection ? output polarity ? speed/power selection ? hysteresis enable ? output synchronization the cm1con1 register (see register 19-2 ) contains control bits for the following: ? interrupt enable ? interrupt edge polarity ? positive input channel selection ? negative input channel selection 19.2.1 comparator enable setting the c1on bit of the cm1con0 register enables the comparator for operation. clearing the c1on bit disables the comparator resulting in minimum current consumption. 19.2.2 comparator output selection the output of the comparator can be monitored by reading either the c1out bit of the cm1con0 register or the mc1out bit of the cmout register. in order to make the output available for an external connection, the following conditions must be true: ? c1oe bit of the cm1con0 register must be set ? corresponding tris bit must be cleared ? c1on bit of the cm1con0 register must be set 19.2.3 comparator output polarity inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. the polarity of the comparator output can be inverted by setting the c1pol bit of the cm1con0 register. clearing the c1pol bit results in a non-inverted output. table 19-2 shows the output state versus input conditions, including polarity control. 19.2.4 comparator speed/power selection the trade-off between speed or power can be opti- mized during program execution with the c1sp control bit. the default state for this bit is ? 1 ? which selects the normal speed mode. device power consumption can be optimized at the cost of slower comparator propaga- tion delay by clearing the c1sp bit to ? 0 ?. note 1: the c1oe bit of the cm1con0 register overrides the port data latch. setting the c1on bit of the cm1con0 register has no impact on the port override. 2: the internal output of the comparator is latched with each instruction cycle. unless otherwise specified, external outputs are not latched. table 19-2: comparator output state vs. input conditions input condition c1pol c1out c1v n > c1v p 00 c1v n < c1v p 01 c1v n > c1v p 11 c1v n < c1v p 10
pic12(l)f1840 ds41441c-page 144 ? 2011-2012 microchip technology inc. 19.3 comparator hysteresis a selectable amount of separation voltage can be added to the input pins of each comparator to provide a hysteresis function to the overall operation. hysteresis is enabled by setting the c1hys bit of the cm1con0 register. see section 30.0 ?electrical specifications? for more information. 19.4 timer1 gate operation the output resulting from a comparator operation can be used as a source for gate control of timer1. see section 21.6 ?timer1 gate? for more information. this feature is useful for timing the duration or interval of an analog event. it is recommended that the comparator output be syn- chronized to timer1. this ensures that timer1 does not increment while a change in the comparator is occur- ring. 19.4.1 comparator output synchronization the output from comparator c1 can be synchronized with timer1 by setting the c1sync bit of the cm1con0 register. once enabled, the comparator output is latched on the falling edge of the timer1 source clock. if a prescaler is used with timer1, the comparator output is latched after the prescaling function. to prevent a race condition, the comparator output is latched on the falling edge of the timer1 clock source and timer1 increments on the rising edge of its clock source. see the comparator block diagram ( figure 19-2 ) and the timer1 block diagram ( figure 21-1 ) for more information. 19.5 comparator interrupt an interrupt can be generated upon a change in the output value of the comparator for each comparator, a rising edge detector and a falling edge detector are present. when either edge detector is triggered and its associ- ated enable bit is set (c1intp and/or c1intn bits of the cm1con1 register), the corresponding interrupt flag bit (c1if bit of the pir2 register) will be set. to enable the interrupt, you must set the following bits: ? c1on, c1pol and c1sp bits of the cm1con0 register ? c1ie bit of the pie2 register ? c1intp bit of the cm1con1 register (for a rising edge detection) ? c1intn bit of the cm1con1 register (for a falling edge detection) ? peie and gie bits of the intcon register the associated interrupt flag bit, c1if bit of the pir2 register, must be cleared in software. if another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. 19.6 comparator positive input selection configuring the c1pch<1:0> bits of the cm1con1 register directs an internal voltage reference or an analog pin to the non-inverting input of the comparator: ? c1in+ analog pin ? dac_output ? fvr (fixed voltage reference) ?v ss (ground) see section 14.0 ?fixed voltage reference (fvr)? for more information on the fixed voltage reference module. see section 17.0 ?digital-to-analog converter (dac) module? for more information on the dac input signal. any time the comparator is disabled (c1on = 0 ), all comparator inputs are disabled. note: although a comparator is disabled, an interrupt can be generated by changing the output polarity with the c1pol bit of the cm1con0 register, or by switching the comparator on or off with the c1on bit of the cm1con0 register.
? 2011-2012 microchip technology inc. ds41441c-page 145 pic12(l)f1840 19.7 comparator negative input selection the c1nch bit of the cm1con1 register directs one of two analog pins to the comparator inverting input. 19.8 comparator response time the comparator output is indeterminate for a period of time after the change of an input source or the selection of a new reference voltage. this period is referred to as the response time. the response time of the comparator differs from the settling time of the voltage reference. therefore, both of these times must be considered when determining the total response time to a comparator input change. see the comparator and voltage refer- ence specifications in section 30.0 ?electrical specifi- cations? for more details. 19.9 interaction with eccp logic the c1 comparator can be used as a general purpose comparator. the output can be brought out to the c1out pin. when the eccp auto-shutdown is active it can use the comparator signal. if auto-restart is also enabled, the comparator can be configured as a closed loop analog feedback to the eccp, thereby, creating an analog controlled pwm. 19.10 analog input connection considerations a simplified circuit for an analog input is shown in figure 19-3 . since the analog input pins share their connection with a digital input, they have reverse biased esd protection diodes to v dd and v ss . the analog input, therefore, must be between v ss and v dd . if the input voltage deviates from this range by more than 0.6v in either direction, one of the diodes is for- ward biased and a latch-up may occur. a maximum source impedance of 10 k ? is recommended for the analog sources. also, any external component connected to an analog input pin, such as a capacitor or a zener diode, should have very little leakage current to minimize inaccuracies introduced. note: to use c1in+ and c1inx- pins as analog input, the appropriate bits must be set in the ansel register and the correspond- ing tris bits must also be set to disable the output drivers. note: when the comparator module is first initialized the output state is unknown. upon initialization, the user should verify the output state of the comparator prior to relying on the result, primarily when using the result in connection with other peripheral features, such as the eccp auto-shutdown mode. note 1: when reading a port register, all pins configured as analog inputs will read as a ? 0 ?. pins configured as digital inputs will convert as an analog input, according to the input specification. 2: analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified.
pic12(l)f1840 ds41441c-page 146 ? 2011-2012 microchip technology inc. figure 19-3: analog input model v a rs < 10k c pin 5 pf v dd v t ? 0.6v v t ? 0.6v r ic i leakage (1) vss legend: c pin = input capacitance i leakage = leakage current at the pin due to various junctions r ic = interconnect resistance r s = source impedance v a = analog voltage v t = threshold voltage to comparator note 1: see section 30.0 ?electrical specifications? . analog input pin
? 2011-2012 microchip technology inc. ds41441c-page 147 pic12(l)f1840 19.11 register definitions: comparator control register 19-1: cm1con0: comparator c1 control register 0 r/w-0/0 r-0/0 r/w-0/0 r/w-0/0 u-0 r/w-1/1 r/w-0/0 r/w-0/0 c1on c1out c1oe c1pol ? c1sp c1hys c1sync bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 c1on: comparator enable bit 1 = comparator is enabled 0 = comparator is disabled and consumes no active power bit 6 c1out: comparator output bit if c1pol = 1 (inverted polarity): 1 = c1vp < c1vn 0 = c1vp > c1vn if c1pol = 0 (non-inverted polarity): 1 = c1vp > c1vn 0 = c1vp < c1vn bit 5 c1oe: comparator output enable bit 1 = c1out is present on the c1out pin. requires that the associated tris bit be cleared to actually drive the pin. not affected by c1on. 0 = c1out is internal only bit 4 c1pol: comparator output polarity select bit 1 = comparator output is inverted 0 = comparator output is not inverted bit 3 unimplemented: read as ? 0 ? bit 2 c1sp: comparator speed/power select bit 1 = comparator operates in normal power, higher speed mode 0 = comparator operates in low-power, low-speed mode bit 1 c1hys: comparator hysteresis enable bit 1 = comparator hysteresis enabled 0 = comparator hysteresis disabled bit 0 c1sync: comparator output synchronous mode bit 1 = comparator output to timer1 and i/o pin is synchronous to changes on timer1 clock source. output updated on the falling edge of timer1 clock source. 0 = comparator output to timer1 and i/o pin is asynchronous.
pic12(l)f1840 ds41441c-page 148 ? 2011-2012 microchip technology inc. table 19-3: summary of registers as sociated with co mparator module register 19-2: cm1con1: comparator c1 control register 1 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 u-0 u-0 r/w-0/0 c1intp c1intn c1pch<1:0> ? ? ? c1nch bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 c1intp: comparator interrupt on positive going edge enable bits 1 = the c1if interrupt flag will be set upon a positive going edge of the c1out bit 0 = no interrupt flag will be set on a positive going edge of the c1out bit bit 6 c1intn: comparator interrupt on negative going edge enable bits 1 = the c1if interrupt flag will be set upon a negative going edge of the c1out bit 0 = no interrupt flag will be set on a negative going edge of the c1out bit bit 5-4 c1pch<1:0>: comparator positive input channel select bits 10 = c1vp connects to fvr voltage reference 01 = c1vp connects to dac voltage reference 00 = c1vp connects to c1in+ pin bit 3-1 unimplemented: read as ? 0 ? bit 0 c1nch: comparator negative input channel select bit 1 = c1vn connects to c1in1- pin 0 = c1vn connects to c1in0- pin register 19-3: cmout: comparator output register u-0 u-0 u-0 u-0 u-0 u-0 u-0 r-0/0 ? ? ? ? ? ? ? mc1out bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-1 unimplemented: read as ? 0 ? bit 0 mc1out: mirror copy of c1out bit name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ansela ? ? ?ansa4 ? ansa2 ansa1 ansa0 106 cm1con0 c1on c1out c1oe c1pol ? c1sp c1hys c1sync 147 cm1con1 c1intp c1intn c1pch<1:0> ? ? ? c1nch 148 cmout ? ? ? ? ? ? ?mc1out 148 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 74 pie2 osfie ? c1ie eeie bcl1ie ? ? ? 76 pir2 osfif ?c1if eeif bcl1if ? ? ? 78 trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 105 legend: ? = unimplemented, read as ? 0 ?. shaded cells are unused by the comparator module.
? 2011-2012 microchip technology inc. ds41441c-page 149 pic12(l)f1840 20.0 timer0 module the timer0 module is an 8-bit timer/counter with the following features: ? 8-bit timer/counter register (tmr0) ? 8-bit prescaler (independent of watchdog timer) ? programmable internal or external clock source ? programmable external clock edge selection ? interrupt on overflow ? tmr0 can be used to gate timer1 figure 20-1 is a block diagram of the timer0 module. 20.1 timer0 operation the timer0 module can be used as either an 8-bit timer or an 8-bit counter. 20.1.1 8-bit timer mode the timer0 module will increment every instruction cycle, if used without a prescaler. 8-bit timer mode is selected by clearing the tmr0cs bit of the option_reg register. when tmr0 is written, the increment is inhibited for two instruction cycles immediately following the write. 20.1.2 8-bit counter mode in 8-bit counter mode, the timer0 module will increment on every rising or falling edge of the t0cki pin or the capacitive sensing oscillator (cpsclk) signal. 8-bit counter mode using the t0cki pin is selected by setting the tmr0cs bit in the option_reg register to ? 1 ? and resetting the t0xcs bit in the cpscon0 register to ? 0 ?. 8-bit counter mode using the capacitive sensing oscillator (cpsclk) signal is selected by setting the tmr0cs bit in the option_reg register to ? 1 ? and setting the t0xcs bit in the cpscon0 register to ? 1 ?. the rising or falling transition of the incrementing edge for either input source is determined by the tmr0se bit in the option_reg register. figure 20-1: block diagra m of the timer0 note: the value written to the tmr0 register can be adjusted, in order to account for the two instruction cycle delay when tmr0 is written. t0cki tmr0se tmr0 ps<2:0> data bus set flag bit tmr0if on overflow tmr0cs 0 1 0 1 8 8 8-bit prescaler f osc /4 psa sync 2 t cy overflow to timer1 1 0 from cpsclk t0xcs
pic12(l)f1840 ds41441c-page 150 ? 2011-2012 microchip technology inc. 20.1.3 software programmable prescaler a software programmable prescaler is available for exclusive use with timer0. the prescaler is enabled by clearing the psa bit of the option_reg register. there are eight prescaler options for the timer0 mod- ule ranging from 1:2 to 1:256. the prescale values are selectable via the ps<2:0> bits of the option_reg register. in order to have a 1:1 prescaler value for the timer0 module, the prescaler must be disabled by set- ting the psa bit of the option_reg register. the prescaler is not readable or writable. all instructions writing to the tmr0 register will clear the prescaler. 20.1.4 timer0 interrupt timer0 will generate an interrupt when the tmr0 register overflows from ffh to 00h. the tmr0if interrupt flag bit of the intcon register is set every time the tmr0 register overflows, regardless of whether or not the timer0 interrupt is enabled. the tmr0if bit can only be cleared in software. the timer0 interrupt enable is the tmr0ie bit of the intcon register. 20.1.5 8-bit counter mode synchronization when in 8-bit counter mode, the incrementing edge on the t0cki pin must be synchronized to the instruction clock. synchronization can be accomplished by sampling the prescaler output on the q2 and q4 cycles of the instruction clock. the high and low periods of the external clocking source must meet the timing requirements as shown in section 30.0 ?electrical specifications? . 20.1.6 operation during sleep timer0 cannot operate while the processor is in sleep mode. the contents of the tmr0 register will remain unchanged while the processor is in sleep mode. note: the watchdog timer (wdt) uses its own independent prescaler. note: the timer0 interrupt cannot wake the processor from sleep since the timer is frozen during sleep.
? 2011-2012 microchip technology inc. ds41441c-page 151 pic12(l)f1840 20.2 register definitions: option register table 20-1: summary of registers associated with timer0 register 20-1: option_reg: option register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 wpuen intedg tmr0cs tmr0se psa ps<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 wpuen : weak pull-up enable bit 1 = all weak pull-ups are disabled (except mclr , if it is enabled) 0 = weak pull-ups are enabled by individual wpua latch values bit 6 intedg: interrupt edge select bit 1 = interrupt on rising edge of int pin 0 = interrupt on falling edge of int pin bit 5 tmr0cs: timer0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (f osc /4) bit 4 tmr0se: timer0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa: prescaler assignment bit 1 = prescaler is not assigned to the timer0 module 0 = prescaler is assigned to the timer0 module bit 2-0 ps<2:0>: prescaler rate select bits name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page cpscon0 cpson cpsrm ? ? cpsrng<1:0> cpsout t0xcs 293 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 74 option_reg wpuen intedg tmr0cs tmr0se psa ps<2:0> 151 tmr0 timer0 module register 149 * trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 105 legend: ? = unimplemented locations, read as ? 0 ?. shaded cells are not used by the timer0 module. * page provides register information. 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 bit value timer0 rate
pic12(l)f1840 ds41441c-page 152 ? 2011-2012 microchip technology inc. notes:
? 2011-2012 microchip technology inc. ds41441c-page 153 pic12(l)f1840 21.0 timer1 module with gate control the timer1 module is a 16-bit timer/counter with the following features: ? 16-bit timer/counter register pair (tmr1h:tmr1l) ? programmable internal or external clock source ? 2-bit prescaler ? dedicated 32 khz oscillator circuit ? optionally synchronized comparator out ? multiple timer1 gate (count enable) sources ? interrupt on overflow ? wake-up on overflow (external clock, asynchronous mode only) ? time base for the capture/compare function ? special event trigger (with eccp) ? selectable gate source polarity ? gate toggle mode ? gate single-pulse mode ? gate value status ? gate event interrupt figure 21-1 is a block diagram of the timer1 module. figure 21-1: timer1 block diagram tmr1h tmr1l t1sync t1ckps<1:0> prescaler 1, 2, 4, 8 0 1 synchronized clock input 2 set flag bit tmr1if on overflow tmr1 (2) tmr1on note 1: st buffer is high speed type when using t1cki. 2: timer1 register increments on rising edge. 3: synchronize does not operate while in sleep. t1g t1osc f osc /4 internal clock t1oso t1osi t1oscen 1 0 t1cki tmr1cs<1:0> (1) synchronize (3) det sleep input tmr1ge 0 1 00 01 10 t1gpol d q ck q 0 1 t1gval t1gtm single pulse acq. control t1gspm t1ggo/done t1gss<1:0> en out 10 11 00 01 f osc internal clock cap. sensing r d en q q1 rd t1gcon data bus det interrupt tmr1gif set t1clk f osc /2 internal clock d en q t1g_in tmr1on oscillator from timer0 overflow reserved to comparator module to clock switching modules
pic12(l)f1840 ds41441c-page 154 ? 2011-2012 microchip technology inc. 21.1 timer1 operation the timer1 module is a 16-bit incrementing counter which is accessed through the tmr1h:tmr1l register pair. writes to tmr1h or tmr1l directly update the counter. when used with an internal clock source, the module is a timer and increments on every instruction cycle. when used with an external clock source, the module can be used as either a timer or counter and incre- ments on every selected edge of the external source. timer1 is enabled by configuring the tmr1on and tmr1ge bits in the t1con and t1gcon registers, respectively. table 21-1 displays the timer1 enable selections. 21.2 clock source selection the tmr1cs<1:0> and t1oscen bits of the t1con register are used to select the clock source for timer1. table 21-2 displays the clock source selections. 21.2.1 internal clock source when the internal clock source is selected, the tmr1h:tmr1l register pair will increment on multiples of f osc as determined by the timer1 prescaler. when the f osc internal clock source is selected, the timer1 register value will in crement by four counts every instruction clock cycle. due to this condition, a 2 lsb error in resolution will occur when reading the timer1 value. to utilize the full resolution of timer1, an asynchronous input signal must be used to gate the timer1 clock input. the following asynchronous sources may be used: ? asynchronous event on the t1g pin to timer1 gate ? c1 comparator input to timer1 gate 21.2.2 external clock source when the external clock source is selected, the timer1 module may work as a timer or a counter. when enabled to count, timer1 is incremented on the rising edge of the external clock input t1cki or the capacitive sensing oscillator signal. either of these external clock sources can be synchronized to the microcontroller system clock or they can run asynchronously. when used as a timer with a clock oscillator, an external 32.768 khz crystal can be used in conjunction with the dedicated internal oscillator circuit. table 21-1: timer1 enable selections tmr1on tmr1ge timer1 operation 00 off 01 off 10 always on 11 count enabled note: in counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: ? timer1 enabled after por ? write to tmr1h or tmr1l ? timer1 is disabled ? timer1 is disabled (tmr1on = 0 ) when t1cki is high then timer1 is enabled (tmr1on= 1 ) when t1cki is low. table 21-2: clock source selections tmr1cs1 tmr1cs0 t1oscen clock source 01x system clock (f osc ) 00x instruction clock (f osc /4) 11x capacitive sensing oscillator 100 external clocking on t1cki pin 101 osc.circuit on t1osi/t1oso pins
? 2011-2012 microchip technology inc. ds41441c-page 155 pic12(l)f1840 21.3 timer1 prescaler timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. the t1ckps bits of the t1con register control the prescale counter. the prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to tmr1h or tmr1l. 21.4 timer1 oscillator a dedicated low-power 32.768 khz oscillator circuit is built-in between pins t1osi (input) and t1oso (amplifier output). this internal circuit is to be used in conjunction with an external 32.768 khz crystal. the oscillator circuit is enabled by setting the t1oscen bit of the t1con register. the oscillator will continue to run during sleep. 21.5 timer1 operation in asynchronous counter mode if the control bit t1sync of the t1con register is set, the external clock input is not synchronized. the timer increments asynchronously to the internal phase clocks. if the external clock source is selected then the timer will continue to run during sleep and can generate an interrupt on overflow, which will wake-up the processor. however, special precautions in software are needed to read/write the timer (see section 21.5.1 ?reading and writing timer1 in asynchronous counter mode? ). 21.5.1 reading and writing timer1 in asynchronous counter mode reading tmr1h or tmr1l while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). however, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. for writes, it is recommended that the user simply stop the timer and write the desired values. a write contention may occur by writing to the timer registers, while the register is incrementing. this may produce an unpredictable value in the tmr1h:tmr1l register pair. 21.6 timer1 gate timer1 can be configured to count freely or the count can be enabled and disabled using timer1 gate circuitry. this is also referred to as timer1 gate enable. timer1 gate can also be driven by multiple selectable sources. 21.6.1 timer1 gate enable the timer1 gate enable mode is enabled by setting the tmr1ge bit of the t1gcon register. the polarity of the timer1 gate enable mode is configured using the t1gpol bit of the t1gcon register. when timer1 gate enable mode is enabled, timer1 will increment on the rising edge of the timer1 clock source. when timer1 gate enable mode is disabled, no incrementing will occur and timer1 will hold the current count. see figure 21-3 for timing details. 21.6.2 timer1 gate source selection timer1 gate source selections are shown in table 21-4 . source selection is controlled by the t1gss bits of the t1gcon register. the polarity for each available source is also selectable. polarity selection is con- trolled by the t1gpol bit of the t1gcon register. table 21-4: timer1 gate sources note: the oscillator requires a start-up and stabilization time before use. thus, t1oscen should be set and a suitable delay observed prior to using timer1. a suitable delay similar to the ost delay can be implemented in software by clearing the tmr1if bit then presetting the tmr1h:tmr1l register pair to fc00h. the tmr1if flag will be set when 1024 clock cycles have elapsed, thereby indicating that the oscillator is running and reasonably stable. note: when switching from synchronous to asynchronous operation, it is possible to skip an increment. when switching from asynchronous to synchronous operation, it is possible to produce an additional increment. table 21-3: timer1 gate enable selections t1clk t1gpol t1g timer1 operation ? 00 counts ? 01 holds count ? 10 holds count ? 11 counts t1gss timer1 gate source 00 timer1 gate pin 01 overflow of timer0 (tmr0 increments from ffh to 00h) 10 comparator 1 output sync_c1out (optionally timer1 synchronized output) 11 reserved
pic12(l)f1840 ds41441c-page 156 ? 2011-2012 microchip technology inc. 21.6.2.1 t1g pin gate operation the t1g pin is one source for timer1 gate control. it can be used to supply an external source to the timer1 gate circuitry. 21.6.2.2 timer0 overflow gate operation when timer0 increments from ffh to 00h, a low-to-high pulse will automatically be generated and internally supplied to the timer1 gate circuitry. 21.6.2.3 comparator c1 gate operation the output resulting from a comparator 1 operation can be selected as a source for timer1 gate control. the comparator 1 output (sync_c1out) can be synchronized to the timer1 clock or left asynchronous. for more information see section 19.4.1 ?comparator output synchronization? . 21.6.3 timer1 gate toggle mode when timer1 gate toggle mode is enabled, it is possi- ble to measure the full-cycle length of a timer1 gate signal, as opposed to the duration of a single level pulse. the timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the sig- nal. see figure 21-4 for timing details. timer1 gate toggle mode is enabled by setting the t1gtm bit of the t1gcon register. when the t1gtm bit is cleared, the flip-flop is cleared and held clear. this is necessary in order to control which edge is measured. 21.6.4 timer1 gate single-pulse mode when timer1 gate single-pulse mode is enabled, it is possible to capture a single-pulse gate event. timer1 gate single-pulse mode is first enabled by setting the t1gspm bit in the t1gcon register. next, the t1ggo/done bit in the t1gcon register must be set. the timer1 will be fully enabled on the next incrementing edge. on the next trailing edge of the pulse, the t1ggo/done bit will automatically be cleared. no other gate events will be allowed to increment timer1 until the t1ggo/done bit is once again set in software. see figure 21-5 for timing details. if the single-pulse gate mode is disabled by clearing the t1gspm bit in the t1gcon register, the t1ggo/done bit should also be cleared. enabling the toggle mode and the single-pulse mode simultaneously will permit both sections to work together. this allows the cycle times on the timer1 gate source to be measured. see figure 21-6 for timing details. 21.6.5 timer1 gate value status when timer1 gate value status is utilized, it is possible to read the most current level of the gate control value. the value is stored in the t1gval bit in the t1gcon register. the t1gval bit is valid even when the timer1 gate is not enabled (tmr1ge bit is cleared). 21.6.6 timer1 gate event interrupt when timer1 gate event interrupt is enabled, it is pos- sible to generate an interrupt upon the completion of a gate event. when the falling edge of t1gval occurs, the tmr1gif flag bit in the pir1 register will be set. if the tmr1gie bit in the pie1 register is set, then an interrupt will be recognized. the tmr1gif flag bit operates even when the timer1 gate is not enabled (tmr1ge bit is cleared). note: enabling toggle mode at the same time as changing the gate polarity may result in indeterminate operation.
? 2011-2012 microchip technology inc. ds41441c-page 157 pic12(l)f1840 21.7 timer1 interrupt the timer1 register pair (tmr1h:tmr1l) increments to ffffh and rolls over to 0000h. when timer1 rolls over, the timer1 interrupt flag bit of the pir1 register is set. to enable the interrupt on rollover, you must set these bits: ? tmr1on bit of the t1con register ? tmr1ie bit of the pie1 register ? peie bit of the intcon register ? gie bit of the intcon register the interrupt is cleared by clearing the tmr1if bit in the interrupt service routine. 21.8 timer1 operation during sleep timer1 can only operate during sleep when setup in asynchronous counter mode. in this mode, an external crystal or clock source can be used to increment the counter. to set up the timer to wake the device: ? tmr1on bit of the t1con register must be set ? tmr1ie bit of the pie1 register must be set ? peie bit of the intcon register must be set ? t1sync bit of the t1con register must be set ? tmr1cs bits of the t1con register must be configured ? t1oscen bit of the t1con register must be configured the device will wake-up on an overflow and execute the next instructions. if the gie bit of the intcon register is set, the device will call the interrupt service routine. timer1 oscillator will continue to operate in sleep regardless of the t1sync bit setting. 21.9 eccp/ccp capture/compare time base the ccp module uses the tmr1h:tmr1l register pair as the time base when operating in capture or compare mode. in capture mode, the value in the tmr1h:tmr1l register pair is copied into the ccpr1h:ccpr1l register pair on a configured event. in compare mode, an event is triggered when the value ccpr1h:ccpr1l register pair matches the value in the tmr1h:tmr1l register pair. this event can be a special event trigger. for more information, see section 24.0 ?capture/compare/pwm modules? . 21.10 eccp/ccp special event trigger when the ccp is configured to trigger a special event, the trigger will clear the tmr1h:tmr1l register pair. this special event does not cause a timer1 interrupt. the ccp module may still be configured to generate a ccp interrupt. in this mode of operation, the ccpr1h:ccpr1l register pair becomes the period register for timer1. timer1 should be synchronized and f osc /4 should be selected as the clock source in order to utilize the spe- cial event trigger. asynchronous operation of timer1 can cause a special event trigger to be missed. in the event that a write to tmr1h or tmr1l coincides with a special event trigger from the ccp, the write will take precedence. for more information, see section 16.2.5 ?special event trigger? . figure 21-2: timer1 incrementing edge note: the tmr1h:tmr1l register pair and the tmr1if bit should be cleared before enabling interrupts. t1cki = 1 when tmr1 enabled t1cki = 0 when tmr1 enabled note 1: arrows indicate counter increments. 2: in counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
pic12(l)f1840 ds41441c-page 158 ? 2011-2012 microchip technology inc. figure 21-3: timer1 gate enable mode figure 21-4: timer1 gate toggle mode tmr1ge t1gpol t1g_in t1cki t1gval timer1 n n + 1 n + 2 n + 3 n + 4 tmr1ge t1gpol t1gtm t1g_in t1cki t1gval timer1 n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8
? 2011-2012 microchip technology inc. ds41441c-page 159 pic12(l)f1840 figure 21-5: timer1 gate single-pulse mode tmr1ge t1gpol t1g_in t1cki t1gval timer1 n n + 1 n + 2 t1gspm t1ggo/ done set by software cleared by hardware on falling edge of t1gval set by hardware on falling edge of t1gval cleared by software cleared by software tmr1gif counting enabled on rising edge of t1g
pic12(l)f1840 ds41441c-page 160 ? 2011-2012 microchip technology inc. figure 21-6: timer1 gate single-pulse and toggle combined mode tmr1ge t1gpol t1g_in t1cki t1gval timer1 nn + 1 n + 2 t1gspm t1ggo/ done set by software cleared by hardware on falling edge of t1gval set by hardware on falling edge of t1gval cleared by software cleared by software tmr1gif t1gtm counting enabled on rising edge of t1g n + 4 n + 3
? 2011-2012 microchip technology inc. ds41441c-page 161 pic12(l)f1840 21.11 register definitions: timer1 control register 21-1: t1con: ti mer1 control register r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w-0/u u-0 r/w-0/u tmr1cs<1:0> t1ckps<1:0> t1oscen t1sync ?tmr1on bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 tmr1cs<1:0>: timer1 clock source select bits 11 = timer1 clock source is capacitive sensing oscillator (caposc) 10 = timer1 clock source is pin or oscillator: if t1oscen = 0 : external clock from t1cki pin (on the rising edge) if t1oscen = 1 : crystal oscillator on t1osi/t1oso pins 01 = timer1 clock source is system clock (f osc ) 00 = timer1 clock source is instruction clock (f osc /4) bit 5-4 t1ckps<1:0>: timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3 t1oscen: lp oscillator enable control bit 1 = dedicated timer1 oscillator circuit enabled 0 = dedicated timer1 oscillator circuit disabled bit 2 t 1sync : timer1 synchronization control bit 1 = do not synchronize asynchronous clock input 0 = synchronize asynchronous clock input with system clock (f osc ) bit 1 unimplemented: read as ? 0 ? bit 0 tmr1on: timer1 on bit 1 = enables timer1 0 = stops timer1 and clears timer1 gate flip-flop
pic12(l)f1840 ds41441c-page 162 ? 2011-2012 microchip technology inc. register 21-2: t1gcon: timer1 gate control register r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w/hc-0/u r-x/x r/w-0/u r/w-0/u tmr1ge t1gpol t1gtm t1gspm t1ggo/ done t1gval t1gss<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared hc = bit is cleared by hardware bit 7 tmr1ge: timer1 gate enable bit if tmr1on = 0 : this bit is ignored if tmr1on = 1 : 1 = timer1 counting is controlled by the timer1 gate function 0 = timer1 counts regardless of timer1 gate function bit 6 t1gpol: timer1 gate polarity bit 1 = timer1 gate is active-high (timer1 counts when gate is high) 0 = timer1 gate is active-low (timer1 counts when gate is low) bit 5 t1gtm: timer1 gate toggle mode bit 1 = timer1 gate toggle mode is enabled 0 = timer1 gate toggle mode is disabled and toggle flip-flop is cleared timer1 gate flip-flop toggles on every rising edge. bit 4 t1gspm: timer1 gate single-pulse mode bit 1 = timer1 gate single-pulse mode is enabled and is controlling timer1 gate 0 = timer1 gate single-pulse mode is disabled bit 3 t1ggo/done : timer1 gate single-pulse acquisition status bit 1 = timer1 gate single-pulse acquisition is ready, waiting for an edge 0 = timer1 gate single-pulse acquisition has completed or has not been started bit 2 t1gval: timer1 gate current state bit indicates the current state of the timer1 gate that could be provided to tmr1h:tmr1l. unaffected by timer1 gate enable (tmr1ge). bit 1-0 t1gss<1:0>: timer1 gate source select bits 11 = reserved 10 = comparator 1 optionally synchronized output (sync_c1out) 01 = timer0 overflow output 00 = timer1 gate pin
? 2011-2012 microchip technology inc. ds41441c-page 163 pic12(l)f1840 table 21-5: summary of registers associated with timer1 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ansela ? ? ? ansa4 ? ansa2 ansa1 ansa0 106 ccp1con p1m<1:0> dc1b<1:0> ccp1m<3:0> 197 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 74 pie1 tmr1gie adie rcie txie ssp1ie ccp1ie tmr2ie tmr1ie 75 pir1 tmr1gif adif rcif txif ssp1if ccp1if tmr2if tmr1if 77 tmr1h holding register for the most significant byte of the 16-bit tmr1 register 157 * tmr1l holding register for the least significant byte of the 16-bit tmr1 register 157 * trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 105 t1con tmr1cs<1:0> t1ckps<1:0> t1oscen t1sync ?tmr1on 161 t1gcon tmr1ge t1gpol t1gtm t1gspm t1ggo/ done t1gval t1gss<1:0> 162 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by the timer1 module. * page provides register information.
pic12(l)f1840 ds41441c-page 164 ? 2011-2012 microchip technology inc. notes:
? 2011-2012 microchip technology inc. ds41441c-page 165 pic12(l)f1840 22.0 timer2 module the timer2 module incorporates the following features: ? 8-bit timer and period registers (tmr2 and pr2, respectively) ? readable and writable (both registers) ? software programmable prescaler (1:1, 1:4, 1:16, and 1:64) ? software programmable postscaler (1:1 to 1:16) ? interrupt on tmr2 match with pr2, respectively ? optional use as the shift clock for the mssp1 modules see figure 22-1 for a block diagram of timer2. figure 22-1: timer2 block diagram comparator tmrx output sets flag bit tmrxif tmrx reset postscaler prescaler prx 2 f osc /4 1:1 to 1:16 1:1, 1:4, 1:16, 1:64 eq 4 txoutps<3:0> txckps<1:0>
pic12(l)f1840 ds41441c-page 166 ? 2011-2012 microchip technology inc. 22.1 timer2 operation the clock input to the timer2 modules is the system instruction clock (f osc /4). tmr2 increments from 00h on each clock edge. a 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. these options are selected by the prescaler control bits, t2ckps<1:0> of the t2con register. the value of tmr2 is compared to that of the period register, pr2, on each clock cycle. when the two values match, the comparator generates a match signal as the timer output. this signal also resets the value of tmr2 to 00h on the next cycle and drives the output counter/postscaler (see section 22.2 ?timer2 interrupt? ). the tmr2 and pr2 registers are both directly readable and writable. the tmr2 register is cleared on any device reset, whereas the pr2 register initializes to ffh. both the prescaler and postscaler counters are cleared on the following events: ? a write to the tmr2 register ? a write to the t2con register ? power-on reset (por) ? brown-out reset (bor) ?mclr reset ? watchdog timer (wdt) reset ? stack overflow reset ? stack underflow reset ? reset instruction 22.2 timer2 interrupt timer2 can also generate an optional device interrupt. the timer2 output signal (tmr2-to-pr2 match) provides the input for the 4-bit counter/postscaler. this counter generates the tmr2 match interrupt flag which is latched in tmr2if of the pir1 register. the interrupt is enabled by setting the tmr2 match interrupt enable bit, tmr2ie of the pie1 register. a range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, t2outps<3:0>, of the t2con register. 22.3 timer2 output the unscaled output of tmr2 is available primarily to the ccp1 module, where it is used as a time base for operations in pwm mode. timer2 can be optionally used as the shift clock source for the mssp1 module operating in spi mode. additional information is provided in section 25.1 ?master ssp (mssp1) module overview? 22.4 timer2 operation during sleep timer2 cannot be operated while the processor is in sleep mode. the contents of the tmr2 and pr2 registers will remain unchanged while the processor is in sleep mode. note: tmr2 is not cleared when t2con is written.
? 2011-2012 microchip technology inc. ds41441c-page 167 pic12(l)f1840 22.5 register definitions: timer2 control register 22-1: t2con: ti mer2 control register u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ? t2outps<3:0> tmr2on t2ckps<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 unimplemented: read as ? 0 ? bit 6-3 t2outps<3:0>: timer output postscaler select bits 1111 = 1:16 postscaler 1110 = 1:15 postscaler 1101 = 1:14 postscaler 1100 = 1:13 postscaler 1011 = 1:12 postscaler 1010 = 1:11 postscaler 1001 = 1:10 postscaler 1000 = 1:9 postscaler 0111 = 1:8 postscaler 0110 = 1:7 postscaler 0101 = 1:6 postscaler 0100 = 1:5 postscaler 0011 = 1:4 postscaler 0010 = 1:3 postscaler 0001 = 1:2 postscaler 0000 = 1:1 postscaler bit 2 tmr2on: timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0 t2ckps<1:0>: timer2 clock prescale select bits 11 = prescaler is 64 10 = prescaler is 16 01 =prescaler is 4 00 =prescaler is 1
pic12(l)f1840 ds41441c-page 168 ? 2011-2012 microchip technology inc. table 22-1: summary of registers associated with timer2 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ccp1con p1m<1:0> dc1b<1:0> ccp1m<3:0> 197 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 74 pie1 tmr1gie adie rcie txie ssp1ie ccp1ie tmr2ie tmr1ie 75 pir1 tmr1gif adif rcif txif ssp1if ccp1if tmr2if tmr1if 77 pr2 timer2 module period register 165 * t2con ? t2outps<3:0> tmr2on t2ckps<1:0> 167 tmr2 holding register for the 8-bit tmr2 register 165 * legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used for timer2 module. * page provides register information.
? 2011-2012 microchip technology inc. ds41441c-page 169 pic12(l)f1840 23.0 data signal modulator the data signal modulator (dsm) is a peripheral which allows the user to mix a data stream, also known as a modulator signal, with a carrier signal to produce a modulated output. both the carrier and the modulator signals are supplied to the dsm module either internally, from the output of a peripheral, or externally through an input pin. the modulated output signal is generated by perform- ing a logical ?and? operation of both the carrier and modulator signals and then provided to the mdout pin. the carrier signal is comprised of two distinct and sep- arate signals. a carrier high (carh) signal and a car- rier low (carl) signal. during the time in which the modulator (mod) signal is in a logic high state, the dsm mixes the carrier high signal with the modulator signal. when the modulator signal is in a logic low state, the dsm mixes the carrier low signal with the modulator signal. using this method, the dsm can generate the following types of key modulation schemes: ? frequency-shift keying (fsk) ? phase-shift keying (psk) ? on-off keying (ook) additionally, the following features are provided within the dsm module: ? carrier synchronization ? carrier source polarity select ? carrier source pin disable ? programmable modulator data ? modulator source pin disable ? modulated output polarity select ? slew rate control figure 23-1 shows a simplified block diagram of the data signal modulator peripheral. figure 23-1: simplified block diagram of the data signal modulator d q mdbit mdmin ccp1 reserved reserved reserved comparator c1 reserved reserved 0000 0001 0010 0011 0100 0101 0110 0111 1000 0011 1001 1010 no channel selected v ss mdcin1 mdcin2 clkr ccp1 reserved 0000 0001 0010 0011 0100 0101 1111 * * no channel selected v ss mdcin1 mdcin2 clkr ccp1 reserved 0000 0001 0010 0011 0100 0101 1111 no channel selected mdch<3:0> mdms<3:0> mdcl<3:0> 1111 * * mssp1 sdo1 reserved eusart sync mdchpol mdclpol d q 1 0 sync 1 0 mdchsync mdclsync mdout mdopol carh carl en mden data signal modulator mod mdoe * * * *
pic12(l)f1840 ds41441c-page 170 ? 2011-2012 microchip technology inc. 23.1 dsm operation the dsm module can be enabled by setting the mden bit in the mdcon register. clearing the mden bit in the mdcon register, disables the dsm module by auto- matically switching the carrier high and carrier low sig- nals to the v ss signal source. the modulator signal source is also switched to the mdbit in the mdcon register. this not only assures that the dsm module is inactive, but that it is also consuming the least amount of current. the values used to select the carrier high, carrier low, and modulator sources held by the modulation source, modulation high carrier, and modulation low carrier control registers are not affected when the mden bit is cleared and the dsm module is disabled. the values inside these registers remain unchanged while the dsm is inactive. the sources for the carrier high, car- rier low and modulator signals will once again be selected when the mden bit is set and the dsm module is again enabled and active. the modulated output signal can be disabled without shutting down the dsm module. the dsm module will remain active and continue to mix signals, but the out- put value will not be sent to the mdout pin. during the time that the output is disabled, the mdout pin will remain low. the modulated output can be disabled by clearing the mdoe bit in the mdcon register. 23.2 modulator signal sources the modulator signal can be supplied from the following sources: ? ccp1 signal ? mssp1 sdo1 signal (spi mode only) ? comparator c1 signal ? eusart tx signal ? external signal on mdmin pin ? mdbit bit in the mdcon register the modulator signal is selected by configuring the mdms <3:0> bits in the mdsrc register. 23.3 carrier signal sources the carrier high signal and carrier low signal can be supplied from the following sources: ? ccp1 signal ? reference clock module signal ? external signal on mdcin1 pin ? external signal on mdcin2 pin ?v ss the carrier high signal is selected by configuring the mdch <3:0> bits in the mdcarh register. the carrier low signal is selected by configuring the mdcl <3:0> bits in the mdcarl register. 23.4 carrier synchronization during the time when the dsm switches between car- rier high and carrier low signal sources, the carrier data in the modulated output signal can become truncated. to prevent this, the carrier signal can be synchronized to the modulator signal. when synchronization is enabled, the carrier pulse that is being mixed at the time of the transition is allowed to transition low before the dsm switches over to the next carrier source. synchronization is enabled separately for the carrier high and carrier low signal sources. synchronization for the carrier high signal can be enabled by setting the mdchsync bit in the mdcarh register. synchroniza- tion for the carrier low signal can be enabled by setting the mdclsync bit in the mdcarl register. figure 23-1 through figure 23-5 show timing diagrams of using various synchronization methods.
? 2011-2012 microchip technology inc. ds41441c-page 171 pic12(l)f1840 figure 23-2: on off keyi ng (ook) synchronization example 23-1: no synchronization (mdshsync = 0 , mdclsync = 0 ) figure 23-3: carrier high synchronization (mdshsync = 1 , mdclsync = 0 ) carrier low (carl) mdchsync = 1 mdclsync = 0 mdchsync = 1 mdclsync = 1 mdchsync = 0 mdclsync = 0 mdchsync = 0 mdclsync = 1 carrier high (carh) modulator (mod) mdchsync = 0 mdclsync = 0 modulator (mod) carrier high (carh) carrier low (carl) active carrier carh carl carl carh state mdchsync = 1 mdclsync = 0 modulator (mod) carrier high (carh) carrier low (carl) active carrier carh carl carl carh state both both
pic12(l)f1840 ds41441c-page 172 ? 2011-2012 microchip technology inc. figure 23-4: carrier low synchronization (mdshsync = 0 , mdclsync = 1 ) figure 23-5: full synchronization (mdshsync = 1 , mdclsync = 1 ) mdchsync = 0 mdclsync = 1 modulator (mod) carrier high (carh) carrier low (carl) active carrier carh carl carl carh state mdchsync = 1 mdclsync = 1 modulator (mod) carrier high (carh) carrier low (carl) active carrier carh carl carl carh state falling edges used to sync
? 2011-2012 microchip technology inc. ds41441c-page 173 pic12(l)f1840 23.5 carrier source polarity select the signal provided from any selected input source for the carrier high and carrier low signals can be inverted. inverting the signal for the carrier high source is enabled by setting the mdchpol bit of the mdcarh register. inverting the signal for the carrier low source is enabled by setting the mdclpol bit of the mdcarl register. 23.6 carrier source pin disable some peripherals assert control over their correspond- ing output pin when they are enabled. for example, when the ccp1 module is enabled, the output of ccp1 is connected to the ccp1 pin. this default connection to a pin can be disabled by set- ting the mdchodis bit in the mdcarh register for the carrier high source and the mdclodis bit in the mdcarl register for the carrier low source. 23.7 programmable modulator data the mdbit of the mdcon register can be selected as the source for the modulator signal. this gives the user the ability to program the value used for modulation. 23.8 modulator source pin disable the modulator source default connection to a pin can be disabled by setting the mdmsodis bit in the mdsrc register. 23.9 modulated output polarity the modulated output signal provided on the mdout pin can also be inverted. inverting the modulated out- put signal is enabled by setting the mdopol bit of the mdcon register. 23.10 slew rate control the slew rate limitation on the output port pin can be disabled. the slew rate limitation can be removed by clearing the mdslr bit in the mdcon register. 23.11 operation in sleep mode the dsm module is not affected by sleep mode. the dsm can still operate during sleep, if the carrier and modulator input sources are also still operable during sleep. 23.12 effects of a reset upon any device reset, the dsm module is disabled. the user?s firmware is responsible for initializing the module before enabling the output. the registers are reset to their default values.
pic12(l)f1840 ds41441c-page 174 ? 2011-2012 microchip technology inc. 23.13 register definitions: modulation control register 23-1: mdcon: modu lation control register r/w-0/0 r/w-0/0 r/w-1/1 r/w-0/0 r-0/0 u-0 u-0 r/w-0/0 mden mdoe mdslr mdopol mdout ? ?mdbit bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 mden: modulator module enable bit 1 = modulator module is enabled and mixing input signals 0 = modulator module is disabled and has no output bit 6 mdoe: modulator module pin output enable bit 1 = modulator pin output enabled 0 = modulator pin output disabled bit 5 mdslr: mdout pin slew rate limiting bit 1 = mdout pin slew rate limiting enabled 0 = mdout pin slew rate limiting disabled bit 4 mdopol: modulator output polarity select bit 1 = modulator output signal is inverted 0 = modulator output signal is not inverted bit 3 mdout: modulator output bit displays the current output value of the modulator module. (1) bit 2-1 unimplemented: read as ? 0 ? bit 0 mdbit: allows software to manually set modulation source input to module (1) 1 = modulator uses high carrier source 0 = modulator uses low carrier source note 1: the modulated output frequency can be greater and asynchronous from the clock that updates this register bit, the bit value may not be valid for higher speed modulator or carrier signals. 2: mdbit must be selected as the modulation source in the mdsrc register for this operation.
? 2011-2012 microchip technology inc. ds41441c-page 175 pic12(l)f1840 register 23-2: mdsrc: modulat ion source control register r/w-x/u u-0 u-0 u-0 r/w-x/u r/w-x/u r/w-x/u r/w-x/u mdmsodis ? ? ?mdms<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 mdmsodis: modulation source output disable bit 1 = output signal driving the peripheral output pin (selected by mdms<3:0>) is disabled 0 = output signal driving the peripheral output pin (selected by mdms<3:0>) is enabled bit 6-4 unimplemented: read as ? 0 ? bit 3-0 mdms<3:0> modulation source selection bits 1111 = reserved. no channel connected. 1110 = reserved. no channel connected. 1101 = reserved. no channel connected. 1100 = reserved. no channel connected. 1011 = reserved. no channel connected. 1010 = eusart tx output. 1001 = reserved. no channel connected. 1000 = mssp1 sdo output 0111 = reserved. no channel connected. 0110 = comparator 1 output 0101 = reserved. no channel connected. 0100 = reserved. no channel connected. 0011 = reserved. no channel connected. 0010 = ccp1 output (pwm output mode only) 0001 = mdmin port pin 0000 = mdbit bit of mdcon register is modulation source note 1: narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
pic12(l)f1840 ds41441c-page 176 ? 2011-2012 microchip technology inc. register 23-3: mdcarh: modulation high carri er control register r/w-x/u r/w-x/u r/w-x/u u-0 r/w-x/u r/w-x/u r/w-x/u r/w-x/u mdchodis mdchpol mdchsync ? mdch<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 mdchodis: modulator high carrier output disable bit 1 = output signal driving the peripheral output pin (selected by mdch<3:0>) is disabled 0 = output signal driving the peripheral output pin (selected by mdch<3:0>) is enabled bit 6 mdchpol: modulator high carrier polarity select bit 1 = selected high carrier signal is inverted 0 = selected high carrier signal is not inverted bit 5 mdchsync: modulator high carrier synchronization enable bit 1 = modulator waits for a falling edge on the high time carrier signal before allowing a switch to the low time carrier 0 = modulator output is not synchronized to the high time carrier signal (1) bit 4 unimplemented: read as ? 0 ? bit 3-0 mdch<3:0> modulator data high carrier selection bits (1) 1111 = reserved. no channel connected. ? ? ? 0101 = reserved. no channel connected. 0100 = ccp1 output (pwm output mode only) 0011 = reference clock module signal (clkr) 0010 = mdcin2 port pin 0001 = mdcin1 port pin 0000 =v ss note 1: narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
? 2011-2012 microchip technology inc. ds41441c-page 177 pic12(l)f1840 table 23-1: summary of registers associ ated with data signal modulator mode register 23-4: mdcarl: modulatio n low carrier control register r/w-x/u r/w-x/u r/w-x/u u-0 r/w-x/u r/w-x/u r/w-x/u r/w-x/u mdclodis mdclpol mdclsync ? mdcl<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 mdclodis: modulator low carrier output disable bit 1 = output signal driving the peripheral output pin (selected by mdcl<3:0> of the mdcarl register) is disabled 0 = output signal driving the peripheral output pin (selected by mdcl<3:0> of the mdcarl register) is enabled bit 6 mdclpol: modulator low carrier polarity select bit 1 = selected low carrier signal is inverted 0 = selected low carrier signal is not inverted bit 5 mdclsync: modulator low carrier synchronization enable bit 1 = modulator waits for a falling edge on the low time carrier signal before allowing a switch to the high time carrier 0 = modulator output is not synchronized to the low time carrier signal (1) bit 4 unimplemented: read as ? 0 ? bit 3-0 mdcl<3:0> modulator data high carrier selection bits (1) 1111 = reserved. no channel connected. ? ? ? 0101 = reserved. no channel connected. 0100 = ccp1 output (pwm output mode only) 0011 = reference clock module signal 0010 = reserved. no channel connected. 0001 = mdcin1 port pin 0000 =v ss note 1: narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page mdcarh mdchodis mdchpol mdchsync ? mdch<3:0> 176 mdcarl mdclodis mdclpol mdclsync ? mdcl<3:0> 177 mdcon mden mdoe mdslr mdopol mdout ? ? mdbit 174 mdsrc mdmsodis ? ? ? mdms<3:0> 175 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used in the data signal modulator mode.
pic12(l)f1840 ds41441c-page 178 ? 2011-2012 microchip technology inc. notes:
? 2011-2012 microchip technology inc. ds41441c-page 179 pic12(l)f1840 24.0 capture/compare/pwm modules the capture/compare/pwm module is a peripheral which allows the user to time and control different events, and to generate pulse-width modulation (pwm) signals. in capture mode, the peripheral allows the timing of the duration of an event. the compare mode allows the user to trigger an external event when a predetermined amount of time has expired. the pwm mode can generate pulse-width modulated signals of varying frequency and duty cycle. this device contains one enhanced capture/compare/ pwm module (eccp1). the half-bridge eccp module has two available i/o pins. see table 24-1 . table 24-1: pwm resources device name eccp1 pic12(l)f1840 enhanced pwm half-bridge
pic12(l)f1840 ds41441c-page 180 ? 2011-2012 microchip technology inc. 24.1 capture mode capture mode makes use of the 16-bit timer1 resource. when an event occurs on the ccp1 pin, the 16-bit ccpr1h:ccpr1l register pair captures and stores the 16-bit value of the tmr1h:tmr1l register pair, respectively. an event is defined as one of the following and is configured by the ccp1m<3:0> bits of the ccp1con register: ? every falling edge ? every rising edge ? every 4th rising edge ? every 16th rising edge when a capture is made, the interrupt request flag bit ccp1if of the pir1 register is set. the interrupt flag must be cleared in software. if another capture occurs before the value in the ccpr1h, ccpr1l register pair is read, the old captured value is overwritten by the new captured value. figure 24-1 shows a simplified diagram of the capture operation. 24.1.1 ccp1 pin configuration in capture mode, the ccp1 pin should be configured as an input by setting the associated tris control bit. also, the ccp1 pin function can be moved to alternative pins using the apfcon register. refer to section 12.1 ?alternate pin function? for more details. figure 24-1: capture mode operation block diagram 24.1.2 timer1 mode resource timer1 must be running in timer mode or synchronized counter mode for the ccp1 module to use the capture feature. in asynchronous counter mode, the capture operation may not work. see section 21.0 ?timer1 module with gate control? for more information on configuring timer1. 24.1.3 software interrupt mode when the capture mode is changed, a false capture interrupt may be generated. the user should keep the ccp1ie interrupt enable bit of the pie1 register clear to avoid false interrupts. additionally, the user should clear the ccp1if interrupt flag bit of the pir1 register following any change in operating mode. 24.1.4 ccp1 prescaler there are four prescaler settings specified by the ccp1m<3:0> bits of the ccp1con register. whenever the ccp1 module is turned off, or the ccp1 module is not in capture mode, the prescaler counter is cleared. any reset will clear the prescaler counter. switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. to avoid this unexpected operation, turn the module off by clearing the ccp1con register before changing the prescaler. example 24-1 demonstrates the code to perform this function. example 24-1: changing between capture prescalers note: if the ccp1 pin is configured as an output, a write to the port can cause a capture condition. ccpr1h ccpr1l tmr1h tmr1l set flag bit ccp1if (pir1 register) capture enable ccp1m<3:0> prescaler ? 1, 4, 16 and edge detect pin ccp1 system clock (f osc ) note: clocking timer1 from the system clock (f osc ) should not be used in capture mode. in order for capture mode to recognize the trigger event on the ccp1 pin, timer1 must be clocked from the instruction clock (f osc /4) or from an external clock source. banksel ccp1con ;set bank bits to point ;to ccp1con clrf ccp1con ;turn ccp1 module off movlw new_capt_ps ;load the w reg with ;the new prescaler ;move value and ccp1 on movwf ccp1con ;load ccp1con with this ;value
? 2011-2012 microchip technology inc. ds41441c-page 181 pic12(l)f1840 24.1.5 capture during sleep capture mode depends upon the timer1 module for proper operation. there are two options for driving the timer1 module in capture mode. it can be driven by the instruction clock (f osc /4), or by an external clock source. when timer1 is clocked by f osc /4, timer1 will not increment during sleep. when the device wakes from sleep, timer1 will continue from its previous state. capture mode will operate during sleep when timer1 is clocked by an external clock source. 24.1.6 alternate pin locations this module incorporates i/o pins that can be moved to other locations with the use of the alternate pin function register, apfcon. to determine which pins can be moved and what their default locations are upon a reset, see section 12.1 ?alternate pin function? for more information. table 24-2: summary of registers associated with capture name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page apfcon rxdtsel sdosel sssel ? t1gsel txcksel p1bsel ccp1sel 102 ccp1con p1m<1:0> dc1b<1:0> ccp1m<3:0> 197 ccpr1l capture/compare/pwm register 1 low byte (lsb) 180 ccpr1h capture/compare/pwm register 1 high byte (msb) 180 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 74 pie1 tmr1gie adie rcie txie ssp1ie ccp1ie tmr2ie tmr1ie 75 pie2 osfie ? c1ie eeie bcl1ie ? ? ? 76 pir1 tmr1gif adif rcif txif ssp1if ccp1if tmr2if tmr1if 77 pir2 osfif ? c1if eeif bcl1if ? ? ? 78 t1con tmr1cs<1:0> t1ckps<1:0> t1oscen t1sync ?tmr1on 161 t1gcon tmr1ge t1gpol t1gtm t1gspm t1ggo/done t1gval t1gss<1:0> 162 tmr1l holding register for the least significant byte of the 16-bit tmr1 register 157 * tmr1h holding register for the most signifi cant byte of the 16-bit tmr1 register 157 * trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 105 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by capture mode. * page provides register information.
pic12(l)f1840 ds41441c-page 182 ? 2011-2012 microchip technology inc. 24.2 compare mode compare mode makes use of the 16-bit timer1 resource. the 16-bit value of the ccpr1h:ccpr1l register pair is constantly compared against the 16-bit value of the tmr1h:tmr1l register pair. when a match occurs, one of the following events can occur: ? toggle the ccp1 output ? set the ccp1 output ? clear the ccp1 output ? generate a special event trigger ? generate a software interrupt the action on the pin is based on the value of the ccp1m<3:0> control bits of the ccp1con register. at the same time, the interrupt flag ccp1if bit is set. all compare modes can generate an interrupt. figure 24-2 shows a simplified diagram of the compare operation. figure 24-2: compare mode operation block diagram 24.2.1 ccp1 pin configuration the user must configure the ccp1 pin as an output by clearing the associated tris bit. also, the ccp1 pin function can be moved to alternative pins using the apfcon register. refer to section 12.1 ?alternate pin function? for more details. 24.2.2 timer1 mode resource in compare mode, timer1 must be running in either timer mode or synchronized counter mode. the compare operation may not work in asynchronous counter mode. see section 21.0 ?timer1 module with gate control? for more information on configuring timer1. 24.2.3 software interrupt mode when generate software interrupt mode is chosen (ccp1m<3:0> = 1010 ), the ccp1 module does not assert control of the ccp1 pin (see the ccp1con register). 24.2.4 special event trigger when special event trigger mode is chosen (ccp1m<3:0> = 1011 ), the ccp1 module does the following: ? resets timer1 ? starts an adc conversion if adc is enabled the ccp1 module does not assert control of the ccp1 pin in this mode. the special event trigger output of the ccp1 occurs immediately upon a match between the tmr1h, tmr1l register pair and the ccpr1h, ccpr1l register pair. the tmr1h, tmr1l register pair is not reset until the next rising edge of the timer1 clock. the special event trigger output starts an adc conversion (if the adc module is enabled). this allows the ccpr1h, ccpr1l register pair to effectively provide a 16-bit programmable period register for timer1. 24.2.5 compare during sleep the compare mode is dependent upon the system clock (f osc ) for proper operation. since f osc is shut down during sleep mode, the compare mode will not function properly during sleep. note: clearing the ccp1con register will force the ccp1 compare output latch to the default low level. this is not the port i/o data latch. ccpr1h ccpr1l tmr1h tmr1l comparator qs r output logic special event trigger set ccp1if interrupt flag (pir1) match tris ccp1m<3:0> mode select output enable pin ccp1 4 note: clocking timer1 from the system clock (f osc ) should not be used in capture mode. in order for capture mode to recognize the trigger event on the ccp1 pin, timer1 must be clocked from the instruction clock (f osc /4) or from an external clock source. note 1: the special event trigger from the ccp1 module does not set interrupt flag bit tmr1if of the pir1 register. 2: removing the match condition by changing the contents of the ccpr1h and ccpr1l register pair, between the clock edge that generates the special event trigger and the clock edge that generates the timer1 reset, will preclude the reset from occurring.
? 2011-2012 microchip technology inc. ds41441c-page 183 pic12(l)f1840 24.2.6 alternate pin locations this module incorporates i/o pins that can be moved to other locations with the use of the alternate pin function register, apfcon. to determine which pins can be moved and what their default locations are upon a reset, see section 12.1 ?alternate pin function? for more information. table 24-3: summary of regist ers associated with compare name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page apfcon rxdtsel sdosel sssel ? t1gsel txcksel p1bsel ccp1sel 102 ccp1con p1m<1:0> dc1b<1:0> ccp1m<3:0> 197 ccpr1l capture/compare/pwm register 1 low byte (lsb) 180 ccpr1h capture/compare/pwm register 1 high byte (msb) 180 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 74 pie1 tmr1gie adie rcie txie ssp1ie ccp1ie tmr2ie tmr1ie 75 pie2 osfie ? c1ie eeie bcl1ie ? ? ? 76 pir1 tmr1gif adif rcif txif ssp1if ccp1if tmr2if tmr1if 77 pir2 osfif ? c1if eeif bcl1if ? ? ? 78 t1con tmr1cs<1:0> t1ckps<1:0> t1oscen t1sync ?tmr1on 161 t1gcon tmr1ge t1gpol t1gtm t1gspm t1ggo/done t1gval t1gss<1:0> 162 tmr1l holding register for the least significant byte of the 16-bit tmr1 register 157 * tmr1h holding register for the most signifi cant byte of the 16-bit tmr1 register 157 * trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 105 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by compare mode. * page provides register information.
pic12(l)f1840 ds41441c-page 184 ? 2011-2012 microchip technology inc. 24.3 pwm overview pulse-width modulation (pwm) is a scheme that provides power to a load by switching quickly between fully on and fully off states. the pwm signal resembles a square wave where the high portion of the signal is considered the on state and the low portion of the signal is considered the off state. the high portion, also known as the pulse width, can vary in time and is defined in steps. a larger number of steps applied, which lengthens the pulse width, also supplies more power to the load. lowering the number of steps applied, which shortens the pulse width, supplies less power. the pwm period is defined as the duration of one complete cycle or the total amount of on and off time combined. pwm resolution defines the maximum number of steps that can be present in a single pwm period. a higher resolution allows for more precise control of the pulse width time and in turn the power that is applied to the load. the term duty cycle describes the proportion of the on time to the off time and is expressed in percentages, where 0% is fully off and 100% is fully on. a lower duty cycle corresponds to less power applied and a higher duty cycle corresponds to more power applied. figure 24-3 shows a typical waveform of the pwm signal. 24.3.1 standard pwm operation the standard pwm mode generates a pulse-width modulation (pwm) signal on the ccp1 pin with up to 10 bits of resolution. the period, duty cycle, and resolution are controlled by the following registers: ? pr2 registers ? t2con registers ? ccpr1l registers ? ccp1con registers figure 24-4 shows a simplified block diagram of pwm operation. figure 24-3: ccp1 pwm output signal figure 24-4: simplified pwm block diagram note 1: the corresponding tris bit must be cleared to enable the pwm output on the ccp1 pin. 2: clearing the ccp1con register will relinquish control of the ccp1 pin. period pulse width tmr2 = 0 tmr2 = ccpr1h:ccp1con<5:4> tmr2 = pr2 ccpr1l ccpr1h (2) (slave) comparator tmr2 pr2 (1) rq s duty cycle registers ccp1con<5:4> clear timer, toggle ccp1 pin and latch duty cycle note 1: the 8-bit timer tmr2 register is concatenated with the 2-bit internal system clock (f osc ), or 2 bits of the prescaler, to create the 10-bit time base. 2: in pwm mode, ccpr1h is a read-only register. tris ccp1 comparator
? 2011-2012 microchip technology inc. ds41441c-page 185 pic12(l)f1840 24.3.2 setup for pwm operation the following steps should be taken when configuring the ccp1 module for standard pwm operation: 1. disable the ccp1 pin output driver by setting the associated tris bit. 2. load the pr2 register with the pwm period value. 3. configure the ccp1 module for the pwm mode by loading the ccp1con register with the appropriate values. 4. load the ccpr1l register and the dc1b1 bits of the ccp1con register, with the pwm duty cycle value. 5. configure and start timer2: ? clear the tmr2if interrupt flag bit of the pir1 register. see note below. ? configure the t2ckps bits of the t2con register with the timer prescale value. ? enable the timer by setting the tmr2on bit of the t2con register. 6. enable pwm output pin: ? wait until the timer overflows and the tmr2if bit of the pir1 register is set. see note below. ? enable the ccp1 pin output driver by clear- ing the associated tris bit. 24.3.3 pwm period the pwm period is specified by the pr2 register of timer2. the pwm period can be calculated using the formula of equation 24-1 . equation 24-1: pwm period when tmr2 is equal to pr2, the following three events occur on the next increment cycle: ?tmr2 is cleared ? the ccp1 pin is set. (exception: if the pwm duty cycle = 0%, the pin will not be set.) ? the pwm duty cycle is latched from ccpr1l into ccpr1h. 24.3.4 pwm duty cycle the pwm duty cycle is specified by writing a 10-bit value to multiple registers: ccpr1l register and dc1b<1:0> bits of the ccp1con register. the ccpr1l contains the eight msbs and the dc1b<1:0> bits of the ccp1con register contain the two lsbs. ccpr1l and dc1b<1:0> bits of the ccp1con register can be written to at any time. the duty cycle value is not latched into ccpr1h until after the period completes (i.e., a match between pr2 and tmr2 registers occurs). while using the pwm, the ccpr1h register is read-only. equation 24-2 is used to calculate the pwm pulse width. equation 24-3 is used to calculate the pwm duty cycle ratio. equation 24-2: pulse width equation 24-3: duty cycle ratio the ccpr1h register and a 2-bit internal latch are used to double buffer the pwm duty cycle. this double buffering is essential for glitchless pwm operation. the 8-bit timer tmr2 register is concatenated with either the 2-bit internal system clock (f osc ), or 2 bits of the prescaler, to create the 10-bit time base. the system clock is used if the timer2 prescaler is set to 1:1. when the 10-bit time base matches the ccpr1h and 2-bit latch, then the ccp1 pin is cleared (see figure 24-4 ). note: in order to send a complete duty cycle and period on the first pwm output, the above steps must be included in the setup sequence. if it is not critical to start with a complete pwm signal on the first output, then step 6 may be ignored. pwm period pr 2 ?? 1 + ?? 4t osc ? ? ? = (tmr2 prescale value) note 1: t osc = 1/f osc note: the timer postscaler (see section 22.1 ?timer2 operation? ) is not used in the determination of the pwm frequency. pulse width ccpr1l:ccp1con<5:4> ?? ? = t osc ? (tmr2 prescale value) duty cycle ratio ccpr1l:ccp1con<5:4> ?? 4pr 2 1 + ?? ----------------------------------------------------------------------- =
pic12(l)f1840 ds41441c-page 186 ? 2011-2012 microchip technology inc. 24.3.5 pwm resolution the resolution determines the number of available duty cycles for a given period. for example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. the maximum pwm resolution is 10 bits when pr2 is 255. the resolution is a function of the pr2 register value as shown by equation 24-4 . equation 24-4: pwm resolution table 24-4: example pwm frequencies and resolutions (f osc = 32 mhz) table 24-5: example pwm frequencies and resolutions (f osc = 20 mhz) table 24-6: example pwm frequencies and resolutions (f osc = 8 mhz) note: if the pulse width value is greater than the period the assigned pwm pin(s) will remain unchanged. resolution 4pr 2 1 + ?? ?? log 2 ?? log ----------------------------------------- - bits = pwm frequency 1.95 khz 7.81 khz 31.25 khz 125 khz 250 khz 333.3 khz timer prescale 16 4 1 1 1 1 pr2 value 0xff 0xff 0xff 0x3f 0x1f 0x17 maximum resolution (bits) 10 10 10 8 7 6.6 pwm frequency 1.22 khz 4.88 khz 19.53 khz 78.12 khz 156.3 khz 208.3 khz timer prescale 16 4 1 1 1 1 pr2 value 0xff 0xff 0xff 0x3f 0x1f 0x17 maximum resolution (bits) 10 10 10 8 7 6.6 pwm frequency 1.22 khz 4.90 khz 19.61 khz 76.92 khz 153.85 khz 200.0 khz timer prescale 16 4 1 1 1 1 pr2 value 0x65 0x65 0x65 0x19 0x0c 0x09 maximum resolution (bits) 8 8 8 6 5 5
? 2011-2012 microchip technology inc. ds41441c-page 187 pic12(l)f1840 24.3.6 operation in sleep mode in sleep mode, the tmr2 register will not increment and the state of the module will not change. if the ccp1 pin is driving a value, it will continue to drive that value. when the device wakes up, tmr2 will continue from its previous state. 24.3.7 changes in system clock frequency the pwm frequency is derived from the system clock frequency. any changes in the system clock frequency will result in changes to the pwm frequency. see section 5.0 ?oscillator module (with fail-safe clock monitor)? for additional details. 24.3.8 effects of reset any reset will force all ports to input mode and the ccp registers to their reset states. 24.3.9 alternate pin locations this module incorporates i/o pins that can be moved to other locations with the use of the alternate pin function register, apfcon. to determine which pins can be moved and what their default locations are upon a reset, see section 12.1 ?alternate pin function? for more information. table 24-7: summary of registers associated with standard pwm name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page apfcon rxdtsel sdosel sssel ? t1gsel txcksel p1bsel ccp1sel 102 ccp1con p1m<1:0> dc1b<1:0> ccp1m<3:0> 197 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 74 pie1 tmr1gie adie rcie txie ssp1ie ccp1ie tmr2ie tmr1ie 75 pir1 tmr1gif adif rcif txif ssp1if ccp1if tmr2if tmr1if 77 pr2 timer2 period register 165 * t2con ? t2outps<3:0> tmr2on t2ckps<1:0> 167 tmr2 timer2 module register 165 trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 105 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by the pwm. * page provides register information.
pic12(l)f1840 ds41441c-page 188 ? 2011-2012 microchip technology inc. 24.4 pwm (enhanced mode) the enhanced pwm mode generates a pulse-width modulation (pwm) signal on up to two different output pins with up to 10 bits of resolution. the period, duty cycle, and resolution are controlled by the following registers: ? pr2 registers ? t2con registers ? ccpr1l registers ? ccp1con registers the eccp modules have the following additional pwm registers which control auto-shutdown, auto-restart, dead-band delay and pwm steering modes: ? ccp1as registers ? pstr1con registers ? pwm1con registers the enhanced pwm module can generate the following three pwm output modes: ? single pwm ? half-bridge pwm ? single pwm with pwm steering mode to select an enhanced pwm output mode, the p1m bits of the ccp1con register must be configured appropriately. the pwm outputs are multiplexed with i/o pins and are designated p1a and p1b. the polarity of the pwm pins is configurable and is selected by setting the bits ccp1m<3:0> in the ccp1con register appropriately. figure 24-5 shows an example of a simplified block diagram of the enhanced pwm module. table 24-8 shows the pin assignments for various enhanced pwm modes. figure 24-5: example simplified block diagram of the enhanced pwm mode note 1: the corresponding tris bit must be cleared to enable the pwm output on the ccp1 pin. 2: clearing the ccp1con register will relinquish control of the ccp1 pin. 3: any pin not used in the enhanced pwm mode is available for alternate pin functions, if applicable. 4: to prevent the generation of an incomplete waveform when the pwm is first enabled, the eccp module waits until the start of a new pwm period before generating a pwm signal. ccpr1l ccpr1h (slave) comparator tmr2 comparator pr2 (1) rq s duty cycle registers dc1b<1:0> clear timer, toggle pwm pin and latch duty cycle note 1: the 8-bit timer tmr1 register is concatenated with the 2-bit internal q clock, or 2 bits of the prescaler to create the 10-bit time base. trisx ccp1/p1a trisx p1b output controller p1m<1:0> 2 ccp1m<3:0> 4 pwm1con ccp1/p1a p1b
? 2011-2012 microchip technology inc. ds41441c-page 189 pic12(l)f1840 table 24-8: example pin assignments for various pwm enhanced modes figure 24-6: example pwm (enhanced mode) output relationships (active-high state) figure 24-7: example enhanced pwm outp ut relationships (active-low state) eccp mode p1m<1:0> ccp1/p1a p1b single 00 yes (1) yes (1) half-bridge 10 yes yes note 1: pwm steering enables outputs in single mode. 0 period 00 10 signal pr2+1 p1m<1:0> p1a modulated p1a modulated p1b modulated pulse width (single output) (half-bridge) delay delay relationships: ? period = 4 * t osc * (pr2 + 1) * (tmrx prescale value) ? pulse width = t osc * (ccpr1l<7:0>:ccp1con<5:4>) * (tmrx prescale value) ? delay = 4 * t osc * (pwm1con<6:0>) 0 period 00 10 signal pr2+1 p1m<1:0> p1a modulated p1a modulated p1b modulated pulse width (single output) (half-bridge) delay delay relationships: ? period = 4 * t osc * (pr2 + 1) * (tmrx prescale value) ? pulse width = t osc * (ccpr1l<7:0>:ccp1con<5:4>) * (tmrx prescale value) ? delay = 4 * t osc * (pwm1con<6:0>)
pic12(l)f1840 ds41441c-page 190 ? 2011-2012 microchip technology inc. 24.4.1 half-bridge mode in half-bridge mode, two pins are used as outputs to drive push-pull loads. the pwm output signal is output on the ccp1/p1a pin, while the complementary pwm output signal is output on the p1b pin (see figure 24-9 ). this mode can be used for half-bridge applications, as shown in figure 24-9 , or for full-bridge applications, where four power switches are being modulated with two pwm signals. in half-bridge mode, the programmable dead-band delay can be used to prevent shoot-through current in half- bridge power devices. the value of the p1dc<6:0> bits of the pwm1con register sets the number of instruction cycles before the output is driven active. if the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. see section 24.4.4 ?programmable dead-band delay mode? for more details of the dead-band delay operations. since the p1a and p1b outputs are multiplexed with the port data latches, the associated tris bits must be cleared to configure p1a and p1b as outputs. figure 24-8: example of half- bridge pwm output figure 24-9: example of half-bridge applications period pulse width td td (1) p1a (2) p1b (2) td = dead-band delay period (1) (1) note 1: at this time, the tmr2 register is equal to the pr2 register. 2: output signals are shown as active-high. p1a p1b fet driver fet driver load + - + - fet driver fet driver v+ load fet driver fet driver p1a p1b standard half-bridge circuit (?push-pull?) half-bridge output driving a full-bridge circuit
? 2011-2012 microchip technology inc. ds41441c-page 191 pic12(l)f1840 24.4.2 enhanced pwm auto- shutdown mode the pwm mode supports an auto-shutdown mode that will disable the pwm outputs when an external shutdown event occurs. auto-shutdown mode places the pwm output pins into a predetermined state. this mode is used to help prevent the pwm from damaging the application. the auto-shutdown sources are selected using the ccp1as<2:0> bits of the ccp1as register. a shutdown event may be generated by: ?a logic ? 0 ? on the flt0 pin ? comparator c1 ? setting the ccp1ase bit in firmware a shutdown condition is indicated by the ccp1ase (auto-shutdown event status) bit of the ccp1as register. if the bit is a ? 0 ?, the pwm pins are operating normally. if the bit is a ? 1 ?, the pwm outputs are in the shutdown state. when a shutdown event occurs, two things happen: the ccp1ase bit is set to ? 1 ?. the ccp1ase will remain set until cleared in firmware or an auto-restart occurs (see section 24.4.3 ?auto-restart mode? ). the enabled pwm pins are asynchronously placed in their shutdown states. the pwm output pins are grouped into pairs [p1a] and [p 1b. the state of each pin pair is determined by the pss1ac and pss1bd bits of the ccp1as register. each pin pair may be placed into one of three states: ? drive logic ? 1 ? ? drive logic ? 0 ? ? tri-state (high-impedance) figure 24-10: pwm auto-shutdown wi th firmware restart (p1rsen = 0 ) note 1: the auto-shutdown condition is a level- based signal, not an edge-based signal. as long as the level is present, the auto- shutdown will persist. 2: writing to the ccp1ase bit is disabled while an auto-shutdown condition persists. 3: once the auto-shutdown condition has been removed and the pwm restarted (either through firmware or auto-restart) the pwm signal will always restart at the beginning of the next pwm period. shutdown pwm ccp1ase bit activity event shutdown event occurs shutdown event clears pwm resumes pwm period start of pwm period ccp1ase cleared by firmware timer overflow timer overflow timer overflow timer overflow missing pulse (auto-shutdown) missing pulse (ccp1ase not clear) timer overflow
pic12(l)f1840 ds41441c-page 192 ? 2011-2012 microchip technology inc. 24.4.3 auto-restart mode the enhanced pwm can be configured to automati- cally restart the pwm signal once the auto-shutdown condition has been removed. auto-restart is enabled by setting the p1rsen bit in the pwm1con register. if auto-restart is enabled, the ccp1ase bit will remain set as long as the auto-shutdown condition is active. when the auto-shutdown condition is removed, the ccp1ase bit will be cleared via hardware and normal operation will resume. figure 24-11: pwm auto-shutdown with auto-restart (p1rsen = 1 ) shutdown pwm ccp1ase bit activity event shutdown event occurs shutdown event clears pwm period start of pwm period ccp1ase cleared by hardware timer overflow timer overflow timer overflow timer overflow missing pulse (auto-shutdown) missing pulse (ccp1ase not clear) timer overflow pwm resumes
? 2011-2012 microchip technology inc. ds41441c-page 193 pic12(l)f1840 24.4.4 programmable dead-band delay mode in half-bridge applications where all power switches are modulated at the pwm frequency, the power switches normally require more time to turn off than to turn on. if both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches may be on for a short period of time until one switch completely turns off. during this brief interval, a very high current ( shoot-through current ) will flow through both power switches, shorting the bridge supply. to avoid this potentially destructive shoot- through current from flowing during switching, turning on either of the power switches is normally delayed to allow the other switch to completely turn off. in half-bridge mode, a digitally programmable dead- band delay is available to avoid shoot-through current from destroying the bridge power switches. the delay occurs at the signal transition from the non-active state to the active state. see figure 24-12 for illustration. the lower seven bits of the associated pwm1con register ( register 24-3 ) sets the delay period in terms of microcontroller instruction cycles (t cy or 4 t osc ). figure 24-12: example of half- bridge pwm output figure 24-13: example of half-bridge applications period pulse width td td (1) p1a (2) p1b (2) td = dead-band delay period (1) (1) note 1: at this time, the tmr2 register is equal to the pr2 register. 2: output signals are shown as active-high. p1a p1b fet driver fet driver v+ v- load + v - + v - standard half-bridge circuit (?push-pull?)
pic12(l)f1840 ds41441c-page 194 ? 2011-2012 microchip technology inc. 24.4.5 pwm steering mode in single output mode, pwm steering allows any of the pwm pins to be the modulated signal. additionally, the same pwm signal can be simultaneously available on multiple pins. once the single output mode is selected (ccp1m<3:2> = 11 and p1m<1:0> = 00 of the ccp1con register), the user firmware can bring out the same pwm signal to one or two output pins by setting the appropriate str1 bits of the pstr1con register, as shown in tab l e 2 4- 8 . while the pwm steering mode is active, the ccp1m<1:0> bits of the ccp1con register determine the polarity of the output pins. the pwm auto-shutdown operation also applies to pwm steering mode as described in section 24.4.2 ?enhanced pwm auto-shutdown mode? . an auto- shutdown event will only affect pins that have pwm outputs enabled. figure 24-14: simplified steering block diagram 24.4.5.1 steering synchronization the str1sync bit of the pstr1con register gives the user two selections of when the steering event will happen. when the str1sync bit is ? 0 ?, the steering event will happen at the end of the instruction that writes to the pstr1con register. in this case, the output signal at the output pins may be an incomplete pwm waveform. this operation is useful when the user firmware needs to immediately remove a pwm signal from the pin. when the str1sync bit is ? 1 ?, the effective steering update will happen at the beginning of the next pwm period. in this case, steering on/off the pwm output will always produce a complete pwm waveform. figures 24-15 and 24-16 illustrate the timing diagrams of the pwm steering depending on the str1sync setting. 24.4.6 start-up considerations when any pwm mode is used, the application hardware must use the proper external pull-up and/or pull-down resistors on the pwm output pins. the ccp1m<1:0> bits of the ccp1con register allow the user to choose whether the pwm output signals are active-high or active-low for each of the pwm output pins (p1a and p1b). the pwm output polarities must be selected before the pwm pin output drivers are enabled. changing the polarity configuration while the pwm pin output drivers are enable is not recommended since it may result in damage to the application circuits. the p1a and p1b output latches may not be in the proper states when the pwm module is initialized. enabling the pwm pin output drivers at the same time as the enhanced pwm modes may cause damage to the application circuit. the enhanced pwm modes must be enabled in the proper output mode and complete a full pwm cycle before enabling the pwm pin output drivers. the completion of a full pwm cycle is indicated by the tmr2if bit of the pir1 register being set as the second pwm period begins. note: the associated tris bits must be set to output (? 0 ?) to enable the pin output driver in order to see the pwm signal on the pin. 1 0 tris p1a pin port data p1a signal str1a 1 0 tris p1b pin port data str1b note 1: port outputs are configured as shown when the ccp1con register bits p1m<1:0> = 00 and ccp1m<3:2> = 11. 2: single pwm output requires setting at least one of the str1 bits. ccp1m1 ccp1m0 note: when the microcontroller is released from reset, all of the i/o pins are in the high- impedance state. the external circuits must keep the power switch devices in the off state until the microcontroller drives the i/o pins with the proper signal levels or activates the pwm output(s).
? 2011-2012 microchip technology inc. ds41441c-page 195 pic12(l)f1840 figure 24-15: example of steering even t at end of instruction (str1sync = 0) figure 24-16: example of steering event at beginning of instruction (str1sync = 1) pwm p1n = pwm str1 p1 port data pwm period port data pwm port data p1n = pwm str1 p1 port data
pic12(l)f1840 ds41441c-page 196 ? 2011-2012 microchip technology inc. 24.4.7 alternate pin locations this module incorporates i/o pins that can be moved to other locations with the use of the alternate pin function register, apfcon. to determine which pins can be moved and what their default locations are upon a reset, see section 12.1 ?alternate pin function? for more information. table 24-9: summary of registers associated with enhanced pwm name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page apfcon rxdtsel sdosel sssel ? t1gsel txcksel p1bsel ccp1sel 102 ccp1con p1m<1:0> dc1b<1:0> ccp1m<3:0> 197 ccp1as ccp1ase ccp1as<2:0> pss1ac<1:0> pss1bd<1:0> 198 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 74 pie1 tmr1gie adie rcie txie ssp1ie ccp1ie tmr2ie tmr1ie 75 pir1 tmr1gif adif rcif txif ssp1if ccp1if tmr2if tmr1if 77 pr2 timer2 period register 165 * pstr1con ? ? ? str1sync reserved reserved str1b str1a 199 pwm1con p1rsen p1dc<6:0> 199 t2con ? t2outps<3:0> tmr2on t2ckps<1:0> 167 tmr2 timer2 module register 165 trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 105 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by the pwm. * page provides register information.
? 2011-2012 microchip technology inc. ds41441c-page 197 pic12(l)f1840 24.5 register definitions: ccp control register 24-1: ccp1con: ccp1 control register r/w-00 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 p1m<1:0> dc1b<1:0> ccp1m<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other reset ?1? = bit is set ?0? = bit is cleared bit 7-6 p1m<1:0>: enhanced pwm output configuration bits capture mode: unused compare mode: unused pwm mode: i f ccp1m<3:2> = 00 , 01 , 10 : xx = p1a assigned as capture/compare input; p1b assigned as port pins (1) if ccp1m<3:2> = 11 : 11 = reserved 10 = half-bridge output; p1a, p1b modulated with dead-band control 01 = reserved 00 = single output; p1a modulated; p1b assigned as port pins bit 5-4 dc1b<1:0>: pwm duty cycle least significant bits capture mode: unused compare mode: unused pwm mode: these bits are the two lsbs of the pwm duty cycle. the eight msbs are found in ccpr1l. bit 3-0 ccp1m<3:0>: eccp1 mode select bits 1011 = compare mode: special event trigger (ccp1 resets timer, sets ccp1if bit, and starts adc conversion if adc module is enabled) 1010 = compare mode: generate software interrupt only; eccp1 pin reverts to i/o state 1001 = compare mode: initialize eccp1 pin high; clear output on compare match (set ccp1if) 1000 = compare mode: initialize eccp1 pin low; set output on compare match (set ccp1if) 0111 = capture mode: every 16th rising edge 0110 = capture mode: every 4th rising edge 0101 = capture mode: every rising edge 0100 = capture mode: every falling edge 0011 = reserved 0010 = compare mode: toggle output on match 0001 = reserved 0000 = capture/compare/pwm off (resets eccp1 module) pwm mode: 1111 = pwm mode: p1a active-low; p1b active-low 1110 = pwm mode: p1a active-low; p1b active-high 1101 = pwm mode: p1a active-high; p1b active-low 1100 = pwm mode: p1aactive-high; p1b active-high
pic12(l)f1840 ds41441c-page 198 ? 2011-2012 microchip technology inc. register 24-2: ccp1as: ccp1 aut o-shutdown control register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ccp1ase ccp1as<2:0> pss1ac<1:0> pss1bd<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 ccp1ase: ccp1 auto-shutdown event status bit 1 = a shutdown event has occurred; ccp1 outputs are in shutdown state 0 = ccp1 outputs are operating bit 6-4 cc1pas<2:0>: ccp1 auto-shutdown source select bits 111 =v il on flt0 pin or comparator c1 low (1) 110 = reserved 101 =v il on flt0 pin or comparator c1 low (1) 100 =v il on flt0 pin 011 = either comparator c1 output low (1) 010 = reserved 001 = comparator c1 output low (1) 000 = auto-shutdown is disabled bit 3-2 pss1ac<1:0>: pin p1a shutdown state control bits 1x = pin p1a tri-state 01 = drive pin p1a to ? 1 ? 00 = drive pin p1a to ? 0 ? bit 1-0 pss1bd<1:0>: pin p1b shutdown state control bits 1x = pin p1b tri-state 01 = drive pin p1b to ? 1 ? 00 = drive pin p1b to ? 0 ? note 1: if c1sync is enabled, the shutdown will be delayed by timer1.
? 2011-2012 microchip technology inc. ds41441c-page 199 pic12(l)f1840 register 24-3: pwm1con: enhanced pwm control register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 p1rsen p1dc<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 p1rsen: pwm restart enable bit 1 = upon auto-shutdown, the ccp1ase bit clears automatically once the shutdown event goes away; the pwm restarts automatically 0 = upon auto-shutdown, ccp1ase must be cleared in software to restart the pwm bit 6-0 p1dc<6:0>: pwm delay count bits p1dc1 = number of f osc /4 (4 * t osc ) cycles between the scheduled time when a pwm signal should transition active and the actual time it transitions active note 1: bit resets to ? 0 ? with two-speed start-up and lp, xt or hs selected as the oscillator mode or fail-safe mode is enabled. register 24-4: pstr1con: pwm steering control register (1) u-0 u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-1/1 ? ? ?str1sync reserved reserved str1b str1a bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-5 unimplemented: read as ? 0 ? bit 4 str1sync: steering sync bit 1 = output steering update occurs on next pwm period 0 = output steering update occurs at the beginning of the instruction cycle boundary bit 3-2 reserved: read as ? 0 ?. maintain these bits clear. bit 1 str1b: steering enable bit b 1 = p1b pin has the pwm waveform with polarity control from ccp1m<1:0> 0 = p1b pin is assigned to port pin bit 0 str1a: steering enable bit a 1 = p1a pin has the pwm waveform with polarity control from ccp1m<1:0> 0 = p1a pin is assigned to port pin note 1: the pwm steering mode is available only when the ccp1con register bits ccp1m<3:2> = 11 and p1m<1:0> = 00 .
pic12(l)f1840 ds41441c-page 200 ? 2011-2012 microchip technology inc. notes:
? 2011-2012 microchip technology inc. ds41441c-page 201 pic12(l)f1840 25.0 master synchronous serial port module 25.1 master ssp (mssp1) module overview the master synchronous serial port (mssp1) module is a serial interface useful for communicating with other peripheral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, display drivers, a/d converters, etc. the mssp1 module can operate in one of two modes: ? serial peripheral interface (spi) ? inter-integrated circuit (i 2 c?) the spi interface supports the following modes and features: ?master mode ? slave mode ? clock parity ? slave select synchronization (slave mode only) ? daisy-chain connection of slave devices figure 25-1 is a block diagram of the spi interface module. figure 25-1: mssp1 blo ck diagram (spi mode) ( ) read write data bus ssp1sr reg ssp1m<3:0> bit 0 shift clock ss control enable edge select clock select tmr2 output t osc prescaler 4, 16, 64 2 edge select 2 (ckp, cke) 4 tris bit sdo ssp1buf reg sdi ss sck baud rate generator (ssp1add)
pic12(l)f1840 ds41441c-page 202 ? 2011-2012 microchip technology inc. the i 2 c interface supports the following modes and features: ?master mode ? slave mode ? byte nacking (slave mode) ? limited multi-master support ? 7-bit and 10-bit addressing ? start and stop interrupts ? interrupt masking ? clock stretching ? bus collision detection ? general call address matching ?address masking ? address hold and data hold modes ? selectable sda hold times figure 25-2 is a block diagram of the i 2 c interface mod- ule in master mode. figure 25-3 is a diagram of the i 2 c interface module in slave mode. figure 25-2: mssp1 block diagram (i 2 c? master mode) read write ssp1sr start bit, stop bit, start bit detect, ssp1buf internal data bus set/reset: s, p, ssp1stat, wcol, ssp1ov shift clock msb lsb sda acknowledge generate (ssp1con2) stop bit detect write collision detect clock arbitration state counter for end of xmit/rcv scl scl in bus collision sda in receive enable (rcen) clock cntl clock arbitrate/bcol detect (hold off clock source) [ssp1m 3:0] baud rate reset sen, pen (ssp1con2) generator (ssp1add) address match detect set ssp1if, bcl1if
? 2011-2012 microchip technology inc. ds41441c-page 203 pic12(l)f1840 figure 25-3: mssp1 block diagram (i 2 c? slave mode) read write ssp1sr reg match detect ssp1add reg start and stop bit detect ssp1buf reg internal data bus addr match set, reset s, p bits (ssp1stat reg) scl sda shift clock msb lsb ssp1msk reg
pic12(l)f1840 ds41441c-page 204 ? 2011-2012 microchip technology inc. 25.2 spi mode overview the serial peripheral interface (spi) bus is a synchronous serial data communication bus that operates in full-duplex mode. devices communicate in a master/slave environment where the master device initiates the communication. a slave device is controlled through a chip select known as slave select. the spi bus specifies four signal connections: ? serial clock (sck) ? serial data out (sdo) ? serial data in (sdi) ? slave select (ss ) figure 25-1 shows the block diagram of the mssp1 module when operating in spi mode. the spi bus operates with a single master device and one or more slave devices. when multiple slave devices are used, an independent slave select con- nection is required from the master device to each slave device. figure 25-4 shows a typical connection between a master device and multiple slave devices. the master selects only one slave at a time. most slave devices have tri-state outputs so their output signal appears disconnected from the bus when they are not selected. transmissions involve two shift registers, eight bits in size, one in the master and one in the slave. with either the master or the slave device, data is always shifted out one bit at a time, with the most significant bit (msb) shifted out first. at the same time, a new least significant bit (lsb) is shifted into the same register. figure 25-5 shows a typical connection between two processors configured as master and slave devices. data is shifted out of both shift registers on the programmed clock edge and latched on the opposite edge of the clock. the master device transmits information out on its sdo output pin which is connected to, and received by, the slave?s sdi input pin. the slave device transmits infor- mation out on its sdo output pin, which is connected to, and received by, the master?s sdi input pin. to begin communication, the master device first sends out the clock signal. both the master and the slave devices should be configured for the same clock polarity. the master device starts a transmission by sending out the msb from its shift register. the slave device reads this bit from that same line and saves it into the lsb position of its shift register. during each spi clock cycle, a full-duplex data transmission occurs. this means that while the master device is sending out the msb from its shift register (on its sdo pin) and the slave device is reading this bit and saving it as the lsb of its shift register, that the slave device is also sending out the msb from its shift register (on its sdo pin) and the master device is reading this bit and saving it as the lsb of its shift register. after 8 bits have been shifted out, the master and slave have exchanged register values. if there is more data to exchange, the shift registers are loaded with new data and the process repeats itself. whether the data is meaningful or not (dummy data), depends on the application software. this leads to three scenarios for data transmission: ? master sends useful data and slave sends dummy data. ? master sends useful data and slave sends useful data. ? master sends dummy data and slave sends use- ful data. transmissions may involve any number of clock cycles. when there is no more data to be transmitted, the master stops sending the clock signal and it deselects the slave. every slave device connected to the bus that has not been selected through its slave select line must disregard the clock and transmission signals and must not transmit out any data of its own.
? 2011-2012 microchip technology inc. ds41441c-page 205 pic12(l)f1840 figure 25-4: spi master and multiple slave connection 25.2.1 spi mode registers the mssp1 module has five registers for spi mode operation. these are: ? mssp1 status register (ssp1stat) ? mssp1 control register 1 (ssp1con1) ? mssp1 control register 3 (ssp1con3) ? mssp1 data buffer register (ssp1buf) ? mssp1 address register (ssp1add) ? mssp1 shift register (ssp1sr) (not directly accessible) ssp1con1 and ssp1stat are the control and status registers in spi mode operation. the ssp1con1 register is readable and writable. the lower 6 bits of the ssp1stat are read-only. the upper two bits of the ssp1stat are read/write. in one spi master mode, ssp1add can be loaded with a value used in the baud rate generator. more information on the baud rate generator is available in section 25.7 ?baud rate generator? . ssp1sr is the shift register used for shifting data in and out. ssp1buf provides indirect access to the ssp1sr register. ssp1buf is the buffer register to which data bytes are written, and from which data bytes are read. in receive operations, ssp1sr and ssp1buf together create a buffered receiver. when ssp1sr receives a complete byte, it is transferred to ssp1buf and the ssp1if interrupt is set. during transmission, the ssp1buf is not buffered. a write to ssp1buf will write to both ssp1buf and ssp1sr. spi master sck sdo sdi general i/o general i/o general i/o sck sdi sdo ss spi slave #1 sck sdi sdo ss spi slave #2 sck sdi sdo ss spi slave #3
pic12(l)f1840 ds41441c-page 206 ? 2011-2012 microchip technology inc. 25.2.2 spi mode operation when initializing the spi, several options need to be specified. this is done by programming the appropriate control bits (ssp1con1<5:0> and ssp1stat<7:6>). these control bits allow the following to be specified: ? master mode (sck1 is the clock output) ? slave mode (sck1 is the clock input) ? clock polarity (idle state of sck1) ? data input sample phase (middle or end of data output time) ? clock edge (output data on rising/falling edge of sck1) ? clock rate (master mode only) ? slave select mode (slave mode only) to enable the serial port, ssp1 enable bit, ssp1en of the ssp1con1 register must be set. to reset or recon- figure spi mode, clear the ssp1en bit, re-initialize the ssp1conx registers and then set the ssp1en bit. this configures the sdi, sdo, sck and ss pins as serial port pins. for the pins to behave as the serial port function, some must have their data direction bits (in the tris register) appropriately programmed as follows: ? sdi must have corresponding tris bit set ? sdo must have corresponding tris bit cleared ? sck (master mode) must have corresponding tris bit cleared ? sck (slave mode) must have corresponding tris bit set ?ss must have corresponding tris bit set any serial port function that is not desired may be overridden by programming the corresponding data direction (tris) register to the opposite value. the mssp1 consists of a transmit/receive shift register (ssp1sr) and a buffer register (ssp1buf). the ssp1sr shifts the data in and out of the device, msb first. the ssp1buf holds the data that was written to the ssp1sr until the received data is ready. once the 8 bits of data have been received, that byte is moved to the ssp1buf register. then, the buffer full detect bit, bf of the ssp1stat register, and the interrupt flag bit, ssp1if, are set. this double-buffering of the received data (ssp1buf) allows the next byte to start reception before reading the data that was just received. any write to the ssp1buf register during transmission/reception of data will be ignored and the write collision detect bit, wcol, of the ssp1con1 register, will be set. user software must clear the wcol bit to allow the following write(s) to the ssp1buf register to complete successfully. when the application software is expecting to receive valid data, the ssp1buf should be read before the next byte of data to transfer is written to the ssp1buf. the buffer full bit, bf of the ssp1stat register, indicates when ssp1buf has been loaded with the received data (transmission is complete). when the ssp1buf is read, the bf bit is cleared. this data may be irrelevant if the spi is only a transmitter. generally, the mssp1 interrupt is used to determine when the transmission/reception has completed. if the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. the ssp1sr is not directly readable or writable and can only be accessed by addressing the ssp1buf register. additionally, the ssp1stat register indicates the various status conditions.
? 2011-2012 microchip technology inc. ds41441c-page 207 pic12(l)f1840 figure 25-5: spi mast er/slave connection serial input buffer (buf) shift register (ssp1sr) msb lsb sdo sdi processor 1 sck spi master ssp1m<3:0> = 00xx serial input buffer (ssp1buf) shift register (ssp1sr) lsb msb sdi sdo processor 2 sck spi slave ssp1m<3:0> = 010x serial clock ss slave select general i/o (optional) = 1010
pic12(l)f1840 ds41441c-page 208 ? 2011-2012 microchip technology inc. 25.2.3 spi master mode the master can initiate the data transfer at any time because it controls the sck line. the master determines when the slave (processor 2, figure 25-5 ) is to broadcast data by the software protocol. in master mode, the data is transmitted/received as soon as the ssp1buf register is written to. if the spi is only going to receive, the sdo output could be disabled (programmed as an input). the ssp1sr register will continue to shift in the signal present on the sdi pin at the programmed clock rate. as each byte is received, it will be loaded into the ssp1buf register as if a normal received byte (interrupts and status bits appropriately set). the clock polarity is selected by appropriately programming the ckp bit of the ssp1con1 register and the cke bit of the ssp1stat register. this then, would give waveforms for spi communication as shown in figure 25-6 , figure 25-8 , figure 25-9 and figure 25-10 , where the msb is transmitted first. in master mode, the spi clock rate (bit rate) is user programmable to be one of the following: ?f osc /4 (or t cy ) ?f osc /16 (or 4 * t cy ) ?f osc /64 (or 16 * t cy ) ? timer2 output/2 ? fosc/(4 * (ssp1add + 1)) figure 25-6 shows the waveforms for master mode. when the cke bit is set, the sdo data is valid before there is a clock edge on sck. the change of the input sample is shown based on the state of the smp bit. the time when the ssp1buf is loaded with the received data is shown. figure 25-6: spi mode waveform (master mode) sck (ckp = 0 sck (ckp = 1 sck (ckp = 0 sck (ckp = 1 4 clock modes input sample input sample sdi bit 7 bit 0 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 sdi ssp1if (smp = 1 ) (smp = 0 ) (smp = 1 ) cke = 1 ) cke = 0 ) cke = 1 ) cke = 0 ) (smp = 0 ) write to ssp1buf ssp1sr to ssp1buf sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (cke = 0 ) (cke = 1 ) bit 0
? 2011-2012 microchip technology inc. ds41441c-page 209 pic12(l)f1840 25.2.4 spi slave mode in slave mode, the data is transmitted and received as external clock pulses appear on sck. when the last bit is latched, the ssp1if interrupt flag bit is set. before enabling the module in spi slave mode, the clock line must match the proper idle state. the clock line can be observed by reading the sck pin. the idle state is determined by the ckp bit of the ssp1con1 register. while in slave mode, the external clock is supplied by the external clock source on the sck pin. this external clock must meet the minimum high and low times as specified in the electrical specifications. while in sleep mode, the slave can transmit/receive data. the shift register is clocked from the sck pin input and when a byte is received, the device will gen- erate an interrupt. if enabled, the device will wake-up from sleep. 25.2.4.1 daisy-chain configuration the spi bus can sometimes be connected in a daisy-chain configuration. the first slave output is con- nected to the second slave input, the second slave output is connected to the third slave input, and so on. the final slave output is connected to the master input. each slave sends out, during a second group of clock pulses, an exact copy of what was received during the first group of clock pulses. the whole chain acts as one large communication shift register. the daisy-chain feature only requires a single slave select line from the master device. figure 25-7 shows the block diagram of a typical daisy-chain connection when operating in spi mode. in a daisy-chain configuration, only the most recent byte on the bus is required by the slave. setting the boen bit of the ssp1con3 register will enable writes to the ssp1buf register, even if the previous byte has not been read. this allows the software to ignore data that may not apply to it. 25.2.5 slave select synchronization the slave select can also be used to synchronize communication. the slave select line is held high until the master device is ready to communicate. when the slave select line is pulled low, the slave knows that a new transmission is starting. if the slave fails to receive the communication properly, it will be reset at the end of the transmission, when the slave select line returns to a high state. the slave is then ready to receive a new transmission when the slave select line is pulled low again. if the slave select line is not used, there is a risk that the slave will even- tually become out of sync with the master. if the slave misses a bit, it will always be one bit off in future trans- missions. use of the slave select line allows the slave and master to align themselves at the beginning of each transmission. the ss pin allows a synchronous slave mode. the spi must be in slave mode with ss pin control enabled (ssp1con1<3:0> = 0100 ). when the ss pin is low, transmission and reception are enabled and the sdo pin is driven. when the ss pin goes high, the sdo pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. external pull-up/pull-down resistors may be desirable depending on the application. when the spi module resets, the bit counter is forced to ? 0 ?. this can be done by either forcing the ss pin to a high level or clearing the ssp1en bit. note 1: when the spi is in slave mode with ss pin control enabled (ssp1con1<3:0> = 0100 ), the spi module will reset if the ss pin is set to v dd . 2: when the spi is used in slave mode with cke set; the user must enable ss pin control. 3: while operated in spi slave mode the smp bit of the ssp1stat register must remain clear.
pic12(l)f1840 ds41441c-page 210 ? 2011-2012 microchip technology inc. figure 25-7: spi daisy-chain connection figure 25-8: slave select synchronous waveform spi master sck sdo sdi general i/o sck sdi sdo ss spi slave #1 sck sdi sdo ss spi slave #2 sck sdi sdo ss spi slave #3 sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 sdo bit 7 bit 6 bit 7 ssp1if interrupt cke = 0 ) cke = 0 ) write to ssp1buf ssp1sr to ssp1buf ss flag bit 0 bit 7 bit 0 bit 6 ssp1buf to ssp1sr shift register ssp1sr and bit count are reset
? 2011-2012 microchip technology inc. ds41441c-page 211 pic12(l)f1840 figure 25-9: spi mode wavefo rm (slave mode with cke = 0 ) figure 25-10: spi mode wavefo rm (slave mode with cke = 1 ) sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ssp1if interrupt cke = 0 ) cke = 0 ) write to ssp1buf ssp1sr to ssp1buf ss flag optional bit 0 detection active write collision valid sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 bit 0 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ssp1if interrupt cke = 1 ) cke = 1 ) write to ssp1buf ssp1sr to ssp1buf ss flag not optional write collision detection active valid
pic12(l)f1840 ds41441c-page 212 ? 2011-2012 microchip technology inc. 25.2.6 spi operation in sleep mode in spi master mode, module clocks may be operating at a different speed than when in full-power mode; in the case of the sleep mode, all clocks are halted. special care must be taken by the user when the mssp1 clock is much faster than the system clock. in slave mode, when mssp1 interrupts are enabled, after the master completes sending data, an mssp1 interrupt will wake the controller from sleep. if an exit from sleep mode is not desired, mssp1 interrupts should be disabled. in spi master mode, when the sleep mode is selected, all module clocks are halted and the transmis- sion/reception will remain in that state until the device wakes. after the device returns to run mode, the mod- ule will resume transmitting and receiving data. in spi slave mode, the spi transmit/receive shift register operates asynchronously to the device. this allows the device to be placed in sleep mode and data to be shifted into the spi transmit/receive shift register. when all 8 bits have been received, the mssp1 interrupt flag bit will be set and if enabled, will wake the device. table 25-1: summary of registers as sociated with spi operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ansela ? ? ?ansa4 ? ansa2 ansa1 ansa0 106 apfcon rxdtsel sdosel sssel ? t1gsel txcksel p1bsel ccp1sel 102 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 74 pie1 tmr1gie adie rcie txie ssp1ie ccp1ie tmr2ie tmr1ie 75 pir1 tmr1gif adif rcif txif ssp1if ccp1if tmr2if tmr1if 77 ssp1buf synchronous serial port receive buffer/transmit register 205 * ssp1con1 wcol sspov sspen ckp sspm<3:0> 252 ssp1con3 acktim pcie scie boen sdaht sbcde ahen dhen 254 ssp1stat smp cke d/a p s r/w ua bf 250 trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 105 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by the mssp1 in spi mode. * page provides register information. note 1: pic12f/lf1840 only.
? 2011-2012 microchip technology inc. ds41441c-page 213 pic12(l)f1840 25.3 i 2 c mode overview the inter-integrated circuit bus (i 2 c) is a multi-master serial data communication bus. devices communicate in a master/slave environment where the master devices initiate the communication. a slave device is controlled through addressing. the i 2 c bus specifies two signal connections: ? serial clock (scl) ? serial data (sda) figure 25-11 shows the block diagram of the mssp1 module when operating in i 2 c mode. both the scl and sda connections are bidirectional open-drain lines, each requiring pull-up resistors for the supply voltage. pulling the line to ground is considered a logical zero and letting the line float is considered a logical one. figure 25-11 shows a typical connection between two processors configured as master and slave devices. the i 2 c bus can operate with one or more master devices and one or more slave devices. there are four potential modes of operation for a given device: ? master transmit mode (master is transmitting data to a slave) ? master receive mode (master is receiving data from a slave) ?slave transmit mode (slave is transmitting data to a master) ? slave receive mode (slave is receiving data from the master) to begin communication, a master device starts out in master transmit mode. the master device sends out a start bit followed by the address byte of the slave it intends to communicate with. this is followed by a sin- gle read/write bit, which determines whether the mas- ter intends to transmit to or receive data from the slave device. if the requested slave exists on the bus, it will respond with an acknowledge bit, otherwise known as an ack . the master then continues in either transmit mode or receive mode and the slave continues in the comple- ment, either in receive mode or transmit mode, respectively. a start bit is indicated by a high-to-low transition of the sda line while the scl line is held high. address and data bytes are sent out, most significant bit (msb) first. the read/write bit is sent out as a logical one when the master intends to read data from the slave, and is sent out as a logical zero when it intends to write data to the slave. figure 25-11: i 2 c master/ slave connection the acknowledge bit (ack ) is an active-low signal, which holds the sda line low to indicate to the transmit- ter that the slave device has received the transmitted data and is ready to receive more. the transition of a data bit is always performed while the scl line is held low. transitions that occur while the scl line is held high are used to indicate start and stop bits. if the master intends to write to the slave, then it repeat- edly sends out a byte of data, with the slave responding after each byte with an ack bit. in this example, the master device is in master transmit mode and the slave is in slave receive mode. if the master intends to read from the slave, then it repeatedly receives a byte of data from the slave, and responds after each byte with an ack bit. in this exam- ple, the master device is in master receive mode and the slave is slave transmit mode. on the last byte of data communicated, the master device may end the transmission by sending a stop bit. if the master device is in receive mode, it sends the stop bit in place of the last ack bit. a stop bit is indi- cated by a low-to-high transition of the sda line while the scl line is held high. in some cases, the master may want to maintain con- trol of the bus and re-initiate another transmission. if so, the master device may send another start bit in place of the stop bit or last ack bit when it is in receive mode. the i 2 c bus specifies three message protocols; ? single message where a master writes data to a slave. ? single message where a master reads data from a slave. ? combined message where a master initiates a minimum of two writes, or two reads, or a combination of writes and reads, to one or more slaves. master scl sda scl sda slave v dd v dd
pic12(l)f1840 ds41441c-page 214 ? 2011-2012 microchip technology inc. when one device is transmitting a logical one, or letting the line float, and a second device is transmitting a log- ical zero, or holding the line low, the first device can detect that the line is not a logical one. this detection, when used on the scl line, is called clock stretching. clock stretching gives slave devices a mechanism to control the flow of data. when this detection is used on the sda line, it is called arbitration. arbitration ensures that there is only one master device communicating at any single time. 25.3.1 clock stretching when a slave device has not completed processing data, it can delay the transfer of more data through the process of clock stretching. an addressed slave device may hold the scl clock line low after receiving or send- ing a bit, indicating that it is not yet ready to continue. the master that is communicating with the slave will attempt to raise the scl line in order to transfer the next bit, but will detect that the clock line has not yet been released. because the scl connection is open-drain, the slave has the ability to hold that line low until it is ready to continue communicating. clock stretching allows receivers that cannot keep up with a transmitter to control the flow of incoming data. 25.3.2 arbitration each master device must monitor the bus for start and stop bits. if the device detects that the bus is busy, it cannot begin a new message until the bus returns to an idle state. however, two master devices may try to initiate a trans- mission on or about the same time. when this occurs, the process of arbitration begins. each transmitter checks the level of the sda data line and compares it to the level that it expects to find. the first transmitter to observe that the two levels do not match, loses arbitra- tion, and must stop transmitting on the sda line. for example, if one transmitter holds the sda line to a logical one (lets it float) and a second transmitter holds it to a logical zero (pulls it low), the result is that the sda line will be low. the first transmitter then observes that the level of the line is different than expected and concludes that another transmitter is communicating. the first transmitter to notice this difference is the one that loses arbitration and must stop driving the sda line. if this transmitter is also a master device, it also must stop driving the scl line. it then can monitor the lines for a stop condition before trying to reissue its transmission. in the meantime, the other device that has not noticed any difference between the expected and actual levels on the sda line continues with its original transmission. it can do so without any compli- cations, because so far, the transmission appears exactly as expected with no other transmitter disturbing the message. slave transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common. if two master devices are sending a message to two different slave devices at the address stage, the master sending the lower slave address always wins arbitra- tion. when two master devices send messages to the same slave address, and addresses can sometimes refer to multiple slaves, the arbitration process must continue into the data stage. arbitration usually occurs very rarely, but it is a necessary process for proper multi-master support.
? 2011-2012 microchip technology inc. ds41441c-page 215 pic12(l)f1840 25.4 i 2 c mode operation all mssp1 i 2 c communication is byte oriented and shifted out msb first. six sfr registers and 2 interrupt flags interface the module with the pic ? microcon- troller and user software. two pins, sda and scl, are exercised by the module to communicate with other external i 2 c devices. 25.4.1 byte format all communication in i 2 c is done in 9-bit segments. a byte is sent from a master to a slave or vice-versa, followed by an acknowledge bit sent back. after the 8th falling edge of the scl line, the device outputting data on the sda changes that pin to an input and reads in an acknowledge value on the next clock pulse. the clock signal, scl, is provided by the master. data is valid to change while the scl signal is low, and sampled on the rising edge of the clock. changes on the sda line while the scl line is high define special conditions on the bus, explained below. 25.4.2 definition of i 2 c terminology there is language and terminology in the description of i 2 c communication that have definitions specific to i 2 c. that word usage is defined below and may be used in the rest of this document without explana- tion. this table was adapted from the philips i 2 c tm specification. 25.4.3 sda and scl pins selection of any i 2 c mode with the ssp1en bit set, forces the scl and sda pins to be open-drain. these pins should be set by the user to inputs by setting the appropriate tris bits. 25.4.4 sda hold time the hold time of the sda pin is selected by the sdaht bit of the ssp1con3 register. hold time is the time sda is held valid after the falling edge of scl. setting the sdaht bit selects a longer 300 ns minimum hold time and may help on buses with large capacitance. table 25-2: i 2 c bus terms note: data is tied to output zero when an i 2 c mode is enabled. term description transmitter the device which shifts data out onto the bus. receiver the device which shifts data in from the bus. master the device that initiates a transfer, generates clock signals and terminates a transfer. slave the device addressed by the master. multi-master a bus with more than one device that can initiate data transfers. arbitration procedure to ensure that only one master at a time controls the bus. winning arbitration ensures that the message is not corrupted. synchronization procedure to synchronize the clocks of two or more devices on the bus. idle no master is controlling the bus, and both sda and scl lines are high. active any time one or more master devices are controlling the bus. addressed slave slave device that has received a matching address and is actively being clocked by a master. matching address address byte that is clocked into a slave that matches the value stored in ssp1add. write request slave receives a matching address with r/w bit clear, and is ready to clock in data. read request master sends an address byte with the r/w bit set, indicating that it wishes to clock data out of the slave. this data is the next and all following bytes until a restart or stop. clock stretching when a device on the bus hold scl low to stall communication. bus collision any time the sda line is sampled low by the module while it is out- putting and expected high state.
pic12(l)f1840 ds41441c-page 216 ? 2011-2012 microchip technology inc. 25.4.5 start condition the i 2 c specification defines a start condition as a transition of sda from a high to a low state while scl line is high. a start condition is always generated by the master and signifies the transition of the bus from an idle to an active state. figure 25-12 shows wave forms for start and stop conditions. a bus collision can occur on a start condition if the module samples the sda line low before asserting it low. this does not conform to the i 2 c specification that states no bus collision can occur on a start. 25.4.6 stop condition a stop condition is a transition of the sda line from low-to-high state while the scl line is high. 25.4.7 restart condition a restart is valid any time that a stop would be valid. a master can issue a restart if it wishes to hold the bus after terminating the current transfer. a restart has the same effect on the slave that a start would, resetting all slave logic and preparing it to clock in an address. the master may want to address the same or another slave. figure 25-13 shows the wave form for a restart condition. in 10-bit addressing slave mode a restart is required for the master to clock data out of the addressed slave. once a slave has been fully addressed, match- ing both high and low address bytes, the master can issue a restart and the high address byte with the r/w bit set. the slave logic will then hold the clock and prepare to clock out data. after a full match with r/w clear in 10-bit mode, a prior match flag is set and maintained. until a stop condi- tion, a high address with r/w clear, or high address match fails. 25.4.8 start/stop condition interrupt masking the scie and pcie bits of the ssp1con3 register can enable the generation of an interrupt in slave modes that do not typically support this function. slave modes where interrupt on start and stop detect are already enabled, these bits will have no effect. figure 25-12: i 2 c start and stop conditions figure 25-13: i 2 c restart condition note: at least one scl low time must appear before a stop is valid, therefore, if the sda line goes low then high again while the scl line stays high, only the start condition is detected. sda scl p stop condition s start condition change of data allowed change of data allowed restart condition sr change of data allowed change of data allowed
? 2011-2012 microchip technology inc. ds41441c-page 217 pic12(l)f1840 25.4.9 acknowledge sequence the 9th scl pulse for any transferred byte in i 2 c is dedicated as an acknowledge. it allows receiving devices to respond back to the transmitter by pulling the sda line low. the transmitter must release control of the line during this time to shift in the response. the acknowledge (ack ) is an active-low signal, pulling the sda line low indicated to the transmitter that the device has received the transmitted data and is ready to receive more. the result of an ack is placed in the ackstat bit of the ssp1con2 register. slave software, when the ahen and dhen bits are set, allow the user to set the ack value sent back to the transmitter. the ackdt bit of the ssp1con2 reg- ister is set/cleared to determine the response. slave hardware will generate an ack response if the ahen and dhen bits of the ssp1con3 register are clear. there are certain conditions where an ack will not be sent by the slave. if the bf bit of the ssp1stat regis- ter or the ssp1ov bit of the ssp1con1 register are set when a byte is received. when the module is addressed, after the 8th falling edge of scl on the bus, the acktim bit of the ssp1con3 register is set. the acktim bit indicates the acknowledge time of the active bus. the acktim status bit is only active when the ahen bit or dhen bit is enabled. 25.5 i 2 c slave mode operation the mssp1 slave mode operates in one of four modes selected in the ssp1m bits of ssp1con1 register. the modes can be divided into 7-bit and 10-bit addressing mode. 10-bit addressing modes operate the same as 7-bit with some additional overhead for handling the larger addresses. modes with start and stop bit interrupts operate the same as the other modes with ssp1if additionally getting set upon detection of a start, restart, or stop condition. 25.5.1 slave mode addresses the ssp1add register ( register 25-6 ) contains the slave mode address. the first byte received after a start or restart condition is compared against the value stored in this register. if the byte matches, the value is loaded into the ssp1buf register and an interrupt is generated. if the value does not match, the module goes idle and no indication is given to the software that anything happened. the ssp mask register ( register 25-5 ) affects the address matching process. see section 25.5.9 ?ssp1 mask register? for more information. 25.5.1.1 i 2 c slave 7-bit addressing mode in 7-bit addressing mode, the lsb of the received data byte is ignored when determining if there is an address match. 25.5.1.2 i 2 c slave 10-bit addressing mode in 10-bit addressing mode, the first received byte is compared to the binary value of ? 1 1 1 1 0 a9 a8 0 ?. a9 and a8 are the two msb?s of the 10-bit address and stored in bits 2 and 1 of the ssp1add register. after the acknowledge of the high byte the ua bit is set and scl is held low until the user updates ssp1add with the low address. the low address byte is clocked in and all 8 bits are compared to the low address value in ssp1add. even if there is not an address match; ssp1if and ua are set, and scl is held low until ssp1add is updated to receive a high byte again. when ssp1add is updated the ua bit is cleared. this ensures the module is ready to receive the high address byte on the next communication. a high and low address match as a write request is required at the start of all 10-bit addressing communi- cation. a transmission can be initiated by issuing a restart once the slave is addressed, and clocking in the high address with the r/w bit set. the slave hard- ware will then acknowledge the read request and prepare to clock out data. this is only valid for a slave after it has received a complete high and low address byte match.
pic12(l)f1840 ds41441c-page 218 ? 2011-2012 microchip technology inc. 25.5.2 slave reception when the r/w bit of a matching received address byte is clear, the r/w bit of the ssp1stat register is cleared. the received address is loaded into the ssp1buf register and acknowledged. when the overflow condition exists for a received address, then not acknowledge is given. an overflow condition is defined as either bit bf of the ssp1stat register is set, or bit ssp1ov of the ssp1con1 regis- ter is set. the boen bit of the ssp1con3 register modifies this operation. for more information see register 25-4 . an mssp1 interrupt is generated for each transferred data byte. flag bit, ssp1if, must be cleared by soft- ware. when the sen bit of the ssp1con2 register is set, scl will be held low (clock stretch) following each received byte. the clock must be released by setting the ckp bit of the ssp1con1 register, except sometimes in 10-bit mode. see section 25.2.3 ?spi master mode? for more detail. 25.5.2.1 7-bit addressing reception this section describes a standard sequence of events for the mssp1 module configured as an i 2 c slave in 7-bit addressing mode. all decisions made by hard- ware or software and their effect on reception. figure 25-14 and figure 25-15 is used as a visual reference for this description. this is a step by step process of what typically must be done to accomplish i 2 c communication. 1. start bit detected. 2. s bit of ssp1stat is set; ssp1if is set if interrupt on start detect is enabled. 3. matching address with r/w bit clear is received. 4. the slave pulls sda low sending an ack to the master, and sets ssp1if bit. 5. software clears the ssp1if bit. 6. software reads received address from ssp1buf clearing the bf flag. 7. if sen = 1 ; slave software sets ckp bit to release the scl line. 8. the master clocks out a data byte. 9. slave drives sda low sending an ack to the master, and sets ssp1if bit. 10. software clears ssp1if. 11. software reads the received byte from ssp1buf clearing bf. 12. steps 8-12 are repeated for all received bytes from the master. 13. master sends stop condition, setting p bit of ssp1stat, and the bus goes idle. 25.5.2.2 7-bit reception with ahen and dhen slave device reception with ahen and dhen set operate the same as without these options with extra interrupts and clock stretching added after the 8th fall- ing edge of scl. these additional interrupts allow the slave software to decide whether it wants to ack the receive address or data byte, rather than the hard- ware. this functionality adds support for pmbus? that was not present on previous versions of this module. this list describes the steps that need to be taken by slave software to use these options for i 2 c communi- cation. figure 25-16 displays a module using both address and data holding. figure 25-17 includes the operation with the sen bit of the ssp1con2 register set. 1. s bit of ssp1stat is set; ssp1if is set if interrupt on start detect is enabled. 2. matching address with r/w bit clear is clocked in. ssp1if is set and ckp cleared after the 8th falling edge of scl. 3. slave clears the ssp1if. 4. slave can look at the acktim bit of the ssp1con3 register to determine if the ssp1if was after or before the ack. 5. slave reads the address value from ssp1buf, clearing the bf flag. 6. slave sets ack value clocked out to the master by setting ackdt. 7. slave releases the clock by setting ckp. 8. ssp1if is set after an ack , not after a nack. 9. if sen = 1 the slave hardware will stretch the clock after the ack. 10. slave clears ssp1if. 11. ssp1if set and ckp cleared after 8th falling edge of scl for a received data byte. 12. slave looks at acktim bit of ssp1con3 to determine the source of the interrupt. 13. slave reads the received data from ssp1buf clearing bf. 14. steps 7-14 are the same for each received data byte. 15. communication is ended by either the slave sending an ack = 1 , or the master sending a stop condition. if a stop is sent and interrupt on stop detect is disabled, the slave will only know by polling the p bit of the sststat register. note: ssp1if is still set after the 9th falling edge of scl even if there is no clock stretching and bf has been cleared. only if nack is sent to master is ssp1if not set
? 2011-2012 microchip technology inc. ds41441c-page 219 pic12(l)f1840 figure 25-14: i 2 c slave, 7-bit address, reception (sen = 0 , ahen = 0 , dhen = 0 ) receiving address ack receiving data ack receiving data ack = 1 a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sda scl ssp1if bf ssp1ov 12345678 12345678 12345678 9 9 9 ack is not sent. ssp1ov set because ssp1buf is still full. cleared by software first byte of data is available in ssp1buf ssp1buf is read ssp1if set on 9th falling edge of scl cleared by software p bus master sends stop condition s from slave to master
pic12(l)f1840 ds41441c-page 220 ? 2011-2012 microchip technology inc. figure 25-15: i 2 c slave, 7-bit address, reception (sen = 1 , ahen = 0 , dhen = 0 ) sen sen a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sda scl 123456789 123456789 123456789 p ssp1if set on 9th scl is not held ckp is written to ? 1 ? in software, ckp is written to ? 1 ? in software, ack low because falling edge of scl releasing scl ack is not sent. bus master sends ckp ssp1ov bf ssp1if ssp1ov set because ssp1buf is still full. cleared by software first byte of data is available in ssp1buf ack = 1 cleared by software ssp1buf is read clock is held low until ckp is set to ? 1 ? releasing scl stop condition s ack ack receive address receive data receive data r/w= 0
? 2011-2012 microchip technology inc. ds41441c-page 221 pic12(l)f1840 figure 25-16: i 2 c slave, 7-bit address, reception (sen = 0 , ahen = 1 , dhen = 1 ) receiving address receiving data received data p a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sda scl bf ckp s p 12 3 4 56 7 8 9 12345678 9 12345678 master sends stop condition s data is read from ssp1buf cleared by software ssp1if is set on 9th falling edge of scl, after ack ckp set by software, scl is released slave software 9 acktim cleared by hardware in 9th rising edge of scl sets ackdt to not ack when dhen = 1 : ckp is cleared by hardware on 8th falling edge of scl slave software clears ackdt to ack the received byte acktim set by hardware on 8th falling edge of scl when ahen = 1 : ckp is cleared by hardware and scl is stretched address is read from ssbuf acktim set by hardware on 8th falling edge of scl ack master releases sda to slave for ack sequence no interrupt after not ack from slave ack = 1 ack ackdt acktim ssp1if if ahen = 1 : ssp1if is set
pic12(l)f1840 ds41441c-page 222 ? 2011-2012 microchip technology inc. figure 25-17: i 2 c slave, 7-bit address, reception (sen = 1 , ahen = 1 , dhen = 1 ) receiving address receive data receive data a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sda scl ssp1if bf ackdt ckp s p ack s 12 34 5678 9 12 3 4567 8 9 12 345 67 8 9 ack ack cleared by software acktim is cleared by hardware ssp1buf can be set by software, read any time before next byte is loaded release scl on 9th rising edge of scl received address is loaded into ssp1buf slave software clears ackdt to ack r/w = 0 master releases sda to slave for ack sequence the received byte when ahen = 1 ; on the 8th falling edge of scl of an address byte, ckp is cleared acktim is set by hardware on 8th falling edge of scl when dhen = 1 ; on the 8th falling edge of scl of a received data byte, ckp is cleared received data is available on ssp1buf slave sends not ack ckp is not cleared if not ack p master sends stop condition no interrupt after if not ack from slave acktim
? 2011-2012 microchip technology inc. ds41441c-page 223 pic12(l)f1840 25.5.3 slave transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the ssp1stat register is set. the received address is loaded into the ssp1buf register, and an ack pulse is sent by the slave on the ninth bit. following the ack , slave hardware clears the ckp bit and the scl pin is held low (see section 25.5.6 ?clock stretching? for more detail). by stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. the transmit data must be loaded into the ssp1buf register which also loads the ssp1sr register. then the scl pin should be released by setting the ckp bit of the ssp1con1 register. the eight data bits are shifted out on the falling edge of the scl input. this ensures that the sda signal is valid during the scl high time. the ack pulse from the master-receiver is latched on the rising edge of the ninth scl input pulse. this ack value is copied to the ackstat bit of the ssp1con2 register. if ackstat is set (not ack ), then the data transfer is complete. in this case, when the not ack is latched by the slave, the slave goes idle and waits for another occurrence of the start bit. if the sda line was low (ack ), the next transmit data must be loaded into the ssp1buf register. again, the scl pin must be released by setting bit ckp. an mssp1 interrupt is generated for each data transfer byte. the ssp1if bit must be cleared by software and the ssp1stat register is used to determine the status of the byte. the ssp1if bit is set on the falling edge of the ninth clock pulse. 25.5.3.1 slave mode bus collision a slave receives a read request and begins shifting data out on the sda line. if a bus collision is detected and the sbcde bit of the ssp1con3 register is set, the bcl1if bit of the pirx register is set. once a bus collision is detected, the slave goes idle and waits to be addressed again. user software can use the bcl1if bit to handle a slave bus collision. 25.5.3.2 7-bit transmission a master device can transmit a read request to a slave, and then clock data out of the slave. the list below outlines what software for a slave will need to do to accomplish a standard transmission. figure 25-18 can be used as a reference to this list. 1. master sends a start condition on sda and scl. 2. s bit of ssp1stat is set; ssp1if is set if interrupt on start detect is enabled. 3. matching address with r/w bit set is received by the slave setting ssp1if bit. 4. slave hardware generates an ack and sets ssp1if. 5. ssp1if bit is cleared by user. 6. software reads the received address from ssp1buf, clearing bf. 7. r/w is set so ckp was automatically cleared after the ack. 8. the slave software loads the transmit data into ssp1buf. 9. ckp bit is set releasing scl, allowing the mas- ter to clock the data out of the slave. 10. ssp1if is set after the ack response from the master is loaded into the ackstat register. 11. ssp1if bit is cleared. 12. the slave software checks the ackstat bit to see if the master wants to clock out more data. 13. steps 9-13 are repeated for each transmitted byte. 14. if the master sends a not ack ; the clock is not held, but ssp1if is still set. 15. the master sends a restart condition or a stop. 16. the slave is no longer addressed. note 1: if the master ack s the clock will be stretched. 2: ackstat is the only bit updated on the rising edge of scl (9th) rather than the falling.
pic12(l)f1840 ds41441c-page 224 ? 2011-2012 microchip technology inc. figure 25-18: i 2 c slave, 7-bit address, transmission (ahen = 0 ) receiving address automatic transmitting data automatic transmitting data a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 sda scl sspif bf ckp ackstat r/w d/a s p received address when r/w is set r/w is copied from the indicates an address is read from sspbuf scl is always held low after 9th scl falling edge matching address byte has been received masters not ack is copied to ackstat ckp is not held for not ack bf is automatically cleared after 8th falling edge of scl data to transmit is loaded into sspbuf set by software cleared by software ack ack ack r/w = 1 s p master sends stop condition
? 2011-2012 microchip technology inc. ds41441c-page 225 pic12(l)f1840 25.5.3.3 7-bit transmission with address hold enabled setting the ahen bit of the ssp1con3 register enables additional clock stretching and interrupt gen- eration after the 8th falling edge of a received match- ing address. once a matching address has been clocked in, ckp is cleared and the ssp1if interrupt is set. figure 25-19 displays a standard waveform of a 7-bit address slave transmission with ahen enabled. 1. bus starts idle. 2. master sends start condition; the s bit of ssp1stat is set; ssp1if is set if interrupt on start detect is enabled. 3. master sends matching address with r/w bit set. after the 8th falling edge of the scl line the ckp bit is cleared and ssp1if interrupt is gen- erated. 4. slave software clears ssp1if. 5. slave software reads acktim bit of ssp1con3 register, and r/w and d/a of the ssp1stat register to determine the source of the interrupt. 6. slave reads the address value from the ssp1buf register clearing the bf bit. 7. slave software decides from this information if it wishes to ack or not ack and sets the ackdt bit of the ssp1con2 register accordingly. 8. slave sets the ckp bit releasing scl. 9. master clocks in the ack value from the slave. 10. slave hardware automatically clears the ckp bit and sets ssp1if after the ack if the r/w bit is set. 11. slave software clears ssp1if. 12. slave loads value to transmit to the master into ssp1buf setting the bf bit. 13. slave sets the ckp bit, releasing the clock. 14. master clocks out the data from the slave and sends an ack value on the 9th scl pulse. 15. slave hardware copies the ack value into the ackstat bit of the ssp1con2 register. 16. steps 10-15 are repeated for each byte trans- mitted to the master from the slave. 17. if the master sends a not ack the slave releases the bus, allowing the master to send a stop and end the communication. note: ssp1buf cannot be loaded until after the ack. note: master must send a not ack on the last byte to ensure that the slave releases the scl line to receive a stop.
pic12(l)f1840 ds41441c-page 226 ? 2011-2012 microchip technology inc. figure 25-19: i 2 c slave, 7-bit address, transmission (ahen = 1 ) receiving address automatic transmitting data automatic transmitting data a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 sda scl ssp1if bf ackdt ackstat ckp r/w d/a received address is read from ssp1buf bf is automatically cleared after 8th falling edge of scl data to transmit is loaded into ssp1buf cleared by software slave clears ackdt to ack address master?s ack response is copied to ssp1stat ckp not cleared after not ack set by software, releases scl acktim is cleared on 9th rising edge of scl acktim is set on 8th falling edge of scl when ahen = 1 ; ckp is cleared by hardware after receiving matching address. when r/w = 1 ; ckp is always cleared after ack s p master sends stop condition ack r/w = 1 master releases sda to slave for ack sequence ack ack acktim
? 2011-2012 microchip technology inc. ds41441c-page 227 pic12(l)f1840 25.5.4 slave mode 10-bit address reception this section describes a standard sequence of events for the mssp1 module configured as an i 2 c slave in 10-bit addressing mode. figure 25-20 is used as a visual reference for this description. this is a step by step process of what must be done by slave software to accomplish i 2 c communication. 1. bus starts idle. 2. master sends start condition; s bit of ssp1stat is set; ssp1if is set if interrupt on start detect is enabled. 3. master sends matching high address with r/w bit clear; ua bit of the ssp1stat register is set. 4. slave sends ack and ssp1if is set. 5. software clears the ssp1if bit. 6. software reads received address from ssp1buf clearing the bf flag. 7. slave loads low address into ssp1add, releasing scl. 8. master sends matching low address byte to the slave; ua bit is set. 9. slave sends ack and ssp1if is set. 10. slave clears ssp1if. 11. slave reads the received matching address from ssp1buf clearing bf. 12. slave loads high address into ssp1add. 13. master clocks a data byte to the slave and clocks out the slaves ack on the 9th scl pulse; ssp1if is set. 14. if sen bit of ssp1con2 is set, ckp is cleared by hardware and the clock is stretched. 15. slave clears ssp1if. 16. slave reads the received byte from ssp1buf clearing bf. 17. if sen is set the slave sets ckp to release the scl. 18. steps 13-17 repeat for each received byte. 19. master sends stop to end the transmission. 25.5.5 10-bit addressing with address or data hold reception using 10-bit addressing with ahen or dhen set is the same as with 7-bit modes. the only difference is the need to update the ssp1add register using the ua bit. all functionality, specifically when the ckp bit is cleared and scl line is held low are the same. figure 25-21 can be used as a reference of a slave in 10-bit addressing with ahen set. figure 25-22 shows a standard waveform for a slave transmitter in 10-bit addressing mode. note: updates to the ssp1add register are not allowed until after the ack sequence. note: if the low address does not match, ssp1if and ua are still set so that the slave soft- ware can set ssp1add back to the high address. bf is not set because there is no match. ckp is unaffected.
pic12(l)f1840 ds41441c-page 228 ? 2011-2012 microchip technology inc. figure 25-20: i 2 c slave, 10-bit address, reception (sen = 1 , ahen = 0 , dhen = 0 ) ssp1if receive first address byte ack receive second address byte ack receive data ack receive data ack 1 1 1 1 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sda scl ua ckp 1 2345678 912345678 912345678 9 12345678 9 p master sends stop condition cleared by software receive address is software updates ssp1add data is read scl is held low set by software, while ckp = 0 from ssp1buf releasing scl when sen = 1 ; ckp is cleared after 9th falling edge of received byte read from ssp1buf and releases scl when ua = 1 ; if address matches set by hardware on 9th falling edge ssp1add it is loaded into ssp1buf scl is held low s bf
? 2011-2012 microchip technology inc. ds41441c-page 229 pic12(l)f1840 figure 25-21: i 2 c slave, 10-bit address, reception (sen = 0 , ahen = 1 , dhen = 0 ) receive first address byte ua receive second address byte ua receive data ack receive data 1 1 1 1 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 sda scl ssp1if bf ackdt ua ckp acktim 12345678 9 s ack ack 12 345678 9 12345678 91 2 ssp1buf is read from received data ssp1buf can be read anytime before the next received byte cleared by software falling edge of scl not allowed until 9th update to ssp1add is set ckp with software releases scl scl clears ua and releases update of ssp1add, set by hardware on 9th falling edge slave software clears ackdt to ack the received byte if when ahen = 1 ; on the 8th falling edge of scl of an address byte, ckp is cleared acktim is set by hardware on 8th falling edge of scl cleared by software r/w = 0
pic12(l)f1840 ds41441c-page 230 ? 2011-2012 microchip technology inc. figure 25-22: i 2 c slave, 10-bit address, transmission (sen = 0 , ahen = 0 , dhen = 0 ) receiving address ack receiving second address byte sr receive first address byte ack transmitting data byte 1 1 1 1 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 1 1 1 1 0 a9 a8 d7 d6 d5 d4 d3 d2 d1 d0 sda scl ssp1if bf ua ckp r/w d/a 1 2345 6789 1 2345 6789 1 23 4 5 6789 1 23456 789 ack = 1 p master sends stop condition master sends not ack master sends restart event ack r/w = 0 s cleared by software after ssp1add is updated, ua is cleared and scl is released high address is loaded received address is data to transmit is set by software indicates an address when r/w = 1 ; r/w is copied from the set by hardware ua indicates ssp1add ssp1buf loaded with received address must be updated has been received loaded into ssp1buf releases scl masters not ack is copied matching address byte ckp is cleared on 9th falling edge of scl read from ssp1buf back into ssp1add ackstat set by hardware
? 2011-2012 microchip technology inc. ds41441c-page 231 pic12(l)f1840 25.5.6 clock stretching clock stretching occurs when a device on the bus holds the scl line low effectively pausing communica- tion. the slave may stretch the clock to allow more time to handle data or prepare a response for the mas- ter device. a master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching. any stretching done by a slave is invisible to the master software and han- dled by the hardware that generates scl. the ckp bit of the ssp1con1 register is used to con- trol stretching in software. any time the ckp bit is cleared, the module will wait for the scl line to go low and then hold it. setting ckp will release scl and allow more communication. 25.5.6.1 normal clock stretching following an ack if the r/w bit of ssp1stat is set, a read request, the slave hardware will clear ckp. this allows the slave time to update ssp1buf with data to transfer to the master. if the sen bit of ssp1con2 is set, the slave hardware will always stretch the clock after the ack sequence. once the slave is ready; ckp is set by software and communication resumes. 25.5.6.2 10-bit addressing mode in 10-bit addressing mode, when the ua bit is set, the clock is always stretched. this is the only time the scl is stretched without ckp being cleared. scl is released immediately after a write to ssp1add. 25.5.6.3 byte nacking when ahen bit of ssp1con3 is set; ckp is cleared by hardware after the 8th falling edge of scl for a received matching address byte. when dhen bit of ssp1con3 is set; ckp is cleared after the 8th falling edge of scl for received data. stretching after the 8th falling edge of scl allows the slave to look at the received address or data and decide if it wants to ack the received data. 25.5.7 clock synchronization and the ckp bit any time the ckp bit is cleared, the module will wait for the scl line to go low and then hold it. however, clearing the ckp bit will not assert the scl output low until the scl output is already sampled low. there- fore, the ckp bit will not assert the scl line until an external i 2 c master device has already asserted the scl line. the scl output will remain low until the ckp bit is set and all other devices on the i 2 c bus have released scl. this ensures that a write to the ckp bit will not violate the minimum high time requirement for scl (see figure 25-23 ). figure 25-23: clock synchronization timing note 1: the bf bit has no effect on if the clock will be stretched or not. this is different than previous versions of the module that would not stretch the clock, clear ckp, if ssp1buf was read before the 9th falling edge of scl. 2: previous versions of the module did not stretch the clock for a transmission if ssp1buf was loaded before the 9th fall- ing edge of scl. it is now always cleared for read requests. note: previous versions of the module did not stretch the clock if the second address byte did not match. sda scl dx ? ? 1 dx wr q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 ssp1con1 ckp master device releases clock master device asserts clock
pic12(l)f1840 ds41441c-page 232 ? 2011-2012 microchip technology inc. 25.5.8 general call address support the addressing procedure for the i 2 c bus is such that the first byte after the start condition usually deter- mines which device will be the slave addressed by the master device. the exception is the general call address which can address all devices. when this address is used, all devices should, in theory, respond with an acknowledge. the general call address is a reserved address in the i 2 c protocol, defined as address 0x00. when the gcen bit of the ssp1con2 register is set, the slave module will automatically ack the reception of this address regardless of the value stored in ssp1add. after the slave clocks in an address of all zeros with the r/w bit clear, an interrupt is generated and slave software can read ssp1buf and respond. figure 25-24 shows a general call reception sequence. in 10-bit address mode, the ua bit will not be set on the reception of the general call address. the slave will prepare to receive the second byte as data, just as it would in 7-bit mode. if the ahen bit of the ssp1con3 register is set, just as with any other address reception, the slave hard- ware will stretch the clock after the 8th falling edge of scl. the slave must then set its ackdt value and release the clock with communication progressing as it would normally. figure 25-24: slave mode general call address sequence 25.5.9 ssp1 mask register an ssp1 mask (ssp1msk) register ( register 25-5 ) is available in i 2 c slave mode as a mask for the value held in the ssp1sr register during an address comparison operation. a zero (? 0 ?) bit in the ssp1msk register has the effect of making the corresponding bit of the received address a ?don?t care.? this register is reset to all ? 1 ?s upon any reset condition and, therefore, has no effect on standard ssp1 operation until written with a mask value. the ssp1 mask register is active during: ? 7-bit address mode: address compare of a<7:1>. ? 10-bit address mode: address compare of a<7:0> only. the ssp1 mask has no effect during the reception of the first (high) byte of the address. sda scl s sspif bf (sspstat<0>) cleared by software sspbuf is read r/w = 0 ack general call address address is compared to general call address receiving data ack 123456789123456789 d7 d6 d5 d4 d3 d2 d1 d0 after ack , set interrupt gcen (sspcon2<7>) ?1?
? 2011-2012 microchip technology inc. ds41441c-page 233 pic12(l)f1840 25.6 i 2 c master mode master mode is enabled by setting and clearing the appropriate sspm bits in the sspcon1 register and by setting the sspen bit. in master mode, the sda and sck pins must be configured as inputs. the mssp peripheral hardware will override the output driver tris controls when necessary to drive the pins low. master mode of operation is supported by interrupt generation on the detection of the start and stop con- ditions. the stop (p) and start (s) bits are cleared from a reset or when the mssp1 module is disabled. con- trol of the i 2 c bus may be taken when the p bit is set, or the bus is idle. in firmware controlled master mode, user code conducts all i 2 c bus operations based on start and stop bit condition detection. start and stop condition detection is the only active circuitry in this mode. all other communication is done by the user software directly manipulating the sda and scl lines. the following events will cause the ssp1 interrupt flag bit, ssp1if, to be set (ssp1 interrupt, if enabled): ? start condition detected ? stop condition detected ? data transfer byte transmitted/received ? acknowledge transmitted/received ? repeated start generated 25.6.1 i 2 c master mode operation the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since the repeated start condition is also the beginning of the next serial transfer, the i 2 c bus will not be released. in master transmitter mode, serial data is output through sda, while scl outputs the serial clock. the first byte transmitted contains the slave address of the receiving device (7 bits) and the read/write (r/w ) bit. in this case, the r/w bit will be logic ? 0 ?. serial data is transmitted 8 bits at a time. after each byte is transmit- ted, an acknowledge bit is received. start and stop conditions are output to indicate the beginning and the end of a serial transfer. in master receive mode, the first byte transmitted con- tains the slave address of the transmitting device (7 bits) and the r/w bit. in this case, the r/w bit will be logic ? 1 ?. thus, the first byte transmitted is a 7-bit slave address followed by a ? 1 ? to indicate the receive bit. serial data is received via sda, while scl outputs the serial clock. serial data is received 8 bits at a time. after each byte is received, an acknowledge bit is transmit- ted. start and stop conditions indicate the beginning and end of transmission. a baud rate generator is used to set the clock frequency output on scl. see section 25.7 ?baud rate generator? for more detail. note 1: the mssp1 module, when configured in i 2 c master mode, does not allow queue- ing of events. for instance, the user is not allowed to initiate a start condition and immediately write the ssp1buf register to initiate transmission before the start condition is complete. in this case, the ssp1buf will not be written to and the wcol bit will be set, indicating that a write to the ssp1buf did not occur 2: when in master mode, start/stop detec- tion is masked and an interrupt is gener- ated when the sen/pen bit is cleared and the generation is complete.
pic12(l)f1840 ds41441c-page 234 ? 2011-2012 microchip technology inc. 25.6.2 clock arbitration clock arbitration occurs when the master, during any receive, transmit or repeated start/stop condition, releases the scl pin (scl allowed to float high). when the scl pin is allowed to float high, the baud rate gen- erator (brg) is suspended from counting until the scl pin is actually sampled high. when the scl pin is sam- pled high, the baud rate generator is reloaded with the contents of ssp1add<7:0> and begins counting. this ensures that the scl high time will always be at least one brg rollover count in the event that the clock is held low by an external device ( figure 25-25 ). figure 25-25: baud rate generator timing with clock arbitration 25.6.3 wcol status flag if the user writes the ssp1buf when a start, restart, stop, receive or transmit sequence is in progress, the wcol is set and the contents of the buffer are unchanged (the write does not occur). any time the wcol bit is set it indicates that an action on ssp1buf was attempted while the module was not idle. sda scl scl deasserted but slave holds dx ? ? 1 dx brg scl is sampled high, reload takes place and brg starts its count 03h 02h 01h 00h (hold off) 03h 02h reload brg value scl low (clock arbitration) scl allowed to transition high brg decrements on q2 and q4 cycles note: because queueing of events is not allowed, writing to the lower 5 bits of ssp1con2 is disabled until the start condition is complete.
? 2011-2012 microchip technology inc. ds41441c-page 235 pic12(l)f1840 25.6.4 i 2 c master mode start condition timing to initiate a start condition ( figure 25-26 ), the user sets the start enable bit, sen bit of the ssp1con2 register. if the sda and scl pins are sampled high, the baud rate generator is reloaded with the contents of ssp1add<7:0> and starts its count. if scl and sda are both sampled high when the baud rate generator times out (t brg ), the sda pin is driven low. the action of the sda being driven low while scl is high is the start condition and causes the s bit of the ssp1stat1 register to be set. following this, the baud rate generator is reloaded with the contents of ssp1add<7:0> and resumes its count. when the baud rate generator times out (t brg ), the sen bit of the ssp1con2 register will be automatically cleared by hardware; the baud rate generator is suspended, leaving the sda line held low and the start condition is complete. figure 25-26: first start bit timing note 1: if at the beginning of the start condition, the sda and scl pins are already sam- pled low, or if during the start condition, the scl line is sampled low before the sda line is driven low, a bus collision occurs, the bus collision interrupt flag, bcl1if, is set, the start condition is aborted and the i 2 c module is reset into its idle state. 2: the philips i 2 c specification states that a bus collision cannot occur on a start. sda scl s t brg 1st bit 2nd bit t brg sda = 1 , at completion of start bit, scl = 1 write to ssp1buf occurs here t brg hardware clears sen bit t brg write to sen bit occurs here set s bit (ssp1stat<3>) and sets ssp1if bit
pic12(l)f1840 ds41441c-page 236 ? 2011-2012 microchip technology inc. 25.6.5 i 2 c master mode repeated start condition timing a repeated start condition ( figure 25-27 ) occurs when the rsen bit of the ssp1con2 register is programmed high and the master state machine is no longer active. when the rsen bit is set, the scl pin is asserted low. when the scl pin is sampled low, the baud rate generator is loaded and begins counting. the sda pin is released (brought high) for one baud rate generator count (t brg ). when the baud rate generator times out, if sda is sampled high, the scl pin will be deasserted (brought high). when scl is sampled high, the baud rate generator is reloaded and begins counting. sda and scl must be sampled high for one t brg . this action is then followed by assertion of the sda pin (sda = 0 ) for one t brg while scl is high. scl is asserted low. following this, the rsen bit of the ssp1con2 register will be automati- cally cleared and the baud rate generator will not be reloaded, leaving the sda pin held low. as soon as a start condition is detected on the sda and scl pins, the s bit of the ssp1stat register will be set. the ssp1if bit will not be set until the baud rate generator has timed out. figure 25-27: repeat start condition waveform note 1: if rsen is programmed while any other event is in progress, it will not take effect. 2: a bus collision during the repeated start condition occurs if: ? sda is sampled low when scl goes from low-to-high. ? scl goes low before sda is asserted low. this may indicate that another master is attempting to transmit a data ? 1 ?. sda scl repeated start write to ssp1con2 write to ssp1buf occurs here at completion of start bit, hardware clears rsen bit 1st bit s bit set by hardware t brg t brg sda = 1 , sda = 1 , scl (no change) scl = 1 occurs here t brg t brg t brg and sets ssp1if sr
? 2011-2012 microchip technology inc. ds41441c-page 237 pic12(l)f1840 25.6.6 i 2 c master mode transmission transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the ssp1buf register. this action will set the buffer full flag bit, bf, and allow the baud rate generator to begin counting and start the next trans- mission. each bit of address/data will be shifted out onto the sda pin after the falling edge of scl is asserted. scl is held low for one baud rate generator rollover count (t brg ). data should be valid before scl is released high. when the scl pin is released high, it is held that way for t brg . the data on the sda pin must remain stable for that duration and some hold time after the next falling edge of scl. after the eighth bit is shifted out (the falling edge of the eighth clock), the bf flag is cleared and the master releases sda. this allows the slave device being addressed to respond with an ack bit during the ninth bit time if an address match occurred, or if data was received prop- erly. the status of ack is written into the ackstat bit on the rising edge of the ninth clock. if the master receives an acknowledge, the acknowledge status bit, ackstat, is cleared. if not, the bit is set. after the ninth clock, the ssp1if bit is set and the master clock (baud rate generator) is suspended until the next data byte is loaded into the ssp1buf, leaving scl low and sda unchanged ( figure 25-28 ). after the write to the ssp1buf, each bit of the address will be shifted out on the falling edge of scl until all seven address bits and the r/w bit are completed. on the falling edge of the eighth clock, the master will release the sda pin, allowing the slave to respond with an acknowledge. on the falling edge of the ninth clock, the master will sample the sda pin to see if the address was recognized by a slave. the status of the ack bit is loaded into the ackstat status bit of the ssp1con2 register. following the falling edge of the ninth clock transmission of the address, the ssp1if is set, the bf flag is cleared and the baud rate generator is turned off until another write to the ssp1buf takes place, holding scl low and allowing sda to float. 25.6.6.1 bf status flag in transmit mode, the bf bit of the ssp1stat register is set when the cpu writes to ssp1buf and is cleared when all 8 bits are shifted out. 25.6.6.2 wcol status flag if the user writes the ssp1buf when a transmit is already in progress (i.e., ssp1sr is still shifting out a data byte), the wcol bit is set and the contents of the buffer are unchanged (the write does not occur). wcol must be cleared by software before the next transmission. 25.6.6.3 ackstat status flag in transmit mode, the ackstat bit of the ssp1con2 register is cleared when the slave has sent an acknowl- edge (ack = 0 ) and is set when the slave does not acknowledge (ack = 1 ). a slave sends an acknowl- edge when it has recognized its address (including a general call), or when the slave has properly received its data. 25.6.6.4 typical transmit sequence: 1. the user generates a start condition by setting the sen bit of the ssp1con2 register. 2. ssp1if is set by hardware on completion of the start. 3. ssp1if is cleared by software. 4. the mssp1 module will wait the required start time before any other operation takes place. 5. the user loads the ssp1buf with the slave address to transmit. 6. address is shifted out the sda pin until all 8 bits are transmitted. transmission begins as soon as ssp1buf is written to. 7. the mssp1 module shifts in the ack bit from the slave device and writes its value into the ackstat bit of the ssp1con2 register. 8. the mssp1 module generates an interrupt at the end of the ninth clock cycle by setting the ssp1if bit. 9. the user loads the ssp1buf with eight bits of data. 10. data is shifted out the sda pin until all 8 bits are transmitted. 11. the mssp1 module shifts in the ack bit from the slave device and writes its value into the ackstat bit of the ssp1con2 register. 12. steps 8-11 are repeated for all transmitted data bytes. 13. the user generates a stop or restart condition by setting the pen or rsen bits of the ssp1con2 register. interrupt is generated once the stop/restart condition is complete.
pic12(l)f1840 ds41441c-page 238 ? 2011-2012 microchip technology inc. figure 25-28: i 2 c master mode waveform (transmission, 7 or 10-bit address) sda scl ssp1if bf (ssp1stat<0>) sen a7 a6 a5 a4 a3 a2 a1 ack = 0 d7 d6 d5 d4 d3 d2 d1 d0 ack transmitting data or second half r/w = 0 transmit address to slave 123456789 123456789 p cleared by software service routine ssp1buf is written by software from ssp1 interrupt after start condition, sen cleared by hardware s ssp1buf written with 7-bit address and r/w start transmit scl held low while cpu responds to ssp1if sen = 0 of 10-bit address write ssp1con2<0> sen = 1 start condition begins from slave, clear ackstat bit ssp1con2<6> ackstat in ssp1con2 = 1 cleared by software ssp1buf written pen r/w cleared by software
? 2011-2012 microchip technology inc. ds41441c-page 239 pic12(l)f1840 25.6.7 i 2 c master mode reception master mode reception ( figure 25-29 ) is enabled by programming the receive enable bit, rcen bit of the ssp1con2 register. the baud rate generator begins counting and on each rollover, the state of the scl pin changes (high-to-low/low-to-high) and data is shifted into the ssp1sr. after the falling edge of the eighth clock, the receive enable flag is automatically cleared, the con- tents of the ssp1sr are loaded into the ssp1buf, the bf flag bit is set, the ssp1if flag bit is set and the baud rate generator is suspended from counting, holding scl low. the mssp1 is now in idle state awaiting the next command. when the buffer is read by the cpu, the bf flag bit is automatically cleared. the user can then send an acknowledge bit at the end of reception by setting the acknowledge sequence enable, acken bit of the ssp1con2 register. 25.6.7.1 bf status flag in receive operation, the bf bit is set when an address or data byte is loaded into ssp1buf from ssp1sr. it is cleared when the ssp1buf register is read. 25.6.7.2 ssp1ov status flag in receive operation, the ssp1ov bit is set when 8 bits are received into the ssp1sr and the bf flag bit is already set from a previous reception. 25.6.7.3 wcol status flag if the user writes the ssp1buf when a receive is already in progress (i.e., ssp1sr is still shifting in a data byte), the wcol bit is set and the contents of the buffer are unchanged (the write does not occur). 25.6.7.4 typical receive sequence: 1. the user generates a start condition by setting the sen bit of the ssp1con2 register. 2. ssp1if is set by hardware on completion of the start. 3. ssp1if is cleared by software. 4. user writes ssp1buf with the slave address to transmit and the r/w bit set. 5. address is shifted out the sda pin until all 8 bits are transmitted. transmission begins as soon as ssp1buf is written to. 6. the mssp1 module shifts in the ack bit from the slave device and writes its value into the ackstat bit of the ssp1con2 register. 7. the mssp1 module generates an interrupt at the end of the ninth clock cycle by setting the ssp1if bit. 8. user sets the rcen bit of the ssp1con2 register and the master clocks in a byte from the slave. 9. after the 8th falling edge of scl, ssp1if and bf are set. 10. master clears ssp1if and reads the received byte from ssp1uf, clears bf. 11. master sets ack value sent to slave in ackdt bit of the ssp1con2 register and initiates the ack by setting the acken bit. 12. masters ack is clocked out to the slave and ssp1if is set. 13. user clears ssp1if. 14. steps 8-13 are repeated for each received byte from the slave. 15. master sends a not ack or stop to end communication. note: the mssp1 module must be in an idle state before the rcen bit is set or the rcen bit will be disregarded.
pic12(l)f1840 ds41441c-page 240 ? 2011-2012 microchip technology inc. figure 25-29: i 2 c master mode waveform (reception, 7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 12 3 4 5 6 7 8 9 12 3 4 5 678 9 1234 bus master terminates transfer ack receiving data from slave receiving data from slave d0 d1 d2 d3 d4 d5 d6 d7 ack r/w transmit address to slave ssp1if bf ack is not sent write to ssp1con2<0>(sen = 1 ), write to ssp1buf occurs here, ack from slave master configured as a receiver by programming ssp1con2<3> (rcen = 1 ) pen bit = 1 written here data shifted in on falling edge of clk cleared by software start xmit sen = 0 ssp1ov sda = 0 , scl = 1 while cpu (ssp1stat<0>) ack cleared by software cleared by software set ssp1if interrupt at end of receive set p bit (ssp1stat<4>) and ssp1if cleared in software ack from master set ssp1if at end set ssp1if interrupt at end of acknowledge sequence set ssp1if interrupt at end of acknow- ledge sequence of receive set acken, start acknowledge sequence ssp1ov is set because ssp1buf is still full sda = ackdt = 1 rcen cleared automatically rcen = 1 , start next receive write to ssp1con2<4> to start acknowledge sequence sda = ackdt (ssp1con2<5>) = 0 rcen cleared automatically responds to ssp1if acken begin start condition cleared by software sda = ackdt = 0 last bit is shifted into ssp1sr and contents are unloaded into ssp1buf rcen master configured as a receiver by programming ssp1con2<3> (rcen = 1 ) rcen cleared automatically ack from master sda\ = ackdt = 0 rcen cleared automatically
? 2011-2012 microchip technology inc. ds41441c-page 241 pic12(l)f1840 25.6.8 acknowledge sequence timing an acknowledge sequence is enabled by setting the acknowledge sequence enable bit, acken bit of the ssp1con2 register. when this bit is set, the scl pin is pulled low and the contents of the acknowledge data bit are presented on the sda pin. if the user wishes to gen- erate an acknowledge, then the ackdt bit should be cleared. if not, the user should set the ackdt bit before starting an acknowledge sequence. the baud rate generator then counts for one rollover period (t brg ) and the scl pin is deasserted (pulled high). when the scl pin is sampled high (clock arbitration), the baud rate generator counts for t brg . the scl pin is then pulled low. following this, the acken bit is automatically cleared, the baud rate generator is turned off and the mssp1 module then goes into idle mode ( figure 25-30 ). 25.6.8.1 wcol status flag if the user writes the ssp1buf when an acknowledge sequence is in progress, then wcol bit is set and the contents of the buffer are unchanged (the write does not occur). 25.6.9 stop condition timing a stop bit is asserted on the sda pin at the end of a receive/transmit by setting the stop sequence enable bit, pen bit of the ssp1con2 register. at the end of a receive/transmit, the scl line is held low after the falling edge of the ninth clock. when the pen bit is set, the master will assert the sda line low. when the sda line is sampled low, the baud rate generator is reloaded and counts down to ? 0 ?. when the baud rate generator times out, the scl pin will be brought high and one t brg (baud rate generator rollover count) later, the sda pin will be deasserted. when the sda pin is sampled high while scl is high, the p bit of the ssp1stat register is set. a t brg later, the pen bit is cleared and the ssp1if bit is set ( figure 25-31 ). 25.6.9.1 wcol status flag if the user writes the ssp1buf when a stop sequence is in progress, then the wcol bit is set and the contents of the buffer are unchanged (the write does not occur). figure 25-30: acknowledge sequen ce waveform note: t brg = one baud rate generator period. sda scl ssp1if set at acknowledge sequence starts here, write to ssp1con2 acken automatically cleared cleared in t brg t brg the end of receive 8 acken = 1 , ackdt = 0 d0 9 ssp1if software ssp1if set at the end of acknowledge sequence cleared in software ack
pic12(l)f1840 ds41441c-page 242 ? 2011-2012 microchip technology inc. figure 25-31: stop cond ition receive or transmit mode 25.6.10 sleep operation while in sleep mode, the i 2 c slave module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from sleep (if the mssp1 interrupt is enabled). 25.6.11 effects of a reset a reset disables the mssp1 module and terminates the current transfer. 25.6.12 multi-master mode in multi-master mode, the interrupt generation on the detection of the start and stop conditions allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset or when the mssp1 module is disabled. control of the i 2 c bus may be taken when the p bit of the ssp1stat register is set, or the bus is idle, with both the s and p bits clear. when the bus is busy, enabling the ssp interrupt will generate the interrupt when the stop condition occurs. in multi-master operation, the sda line must be monitored for arbitration to see if the signal level is the expected output level. this check is performed by hardware with the result placed in the bcl1if bit. the states where arbitration can be lost are: ? address transfer ? data transfer ? a start condition ? a repeated start condition ? an acknowledge condition 25.6.13 multi -master communication, bus collision and bus arbitration multi-master mode support is achieved by bus arbitra- tion. when the master outputs address/data bits onto the sda pin, arbitration takes place when the master outputs a ? 1 ? on sda, by letting sda float high and another master asserts a ? 0 ?. when the scl pin floats high, data should be stable. if the expected data on sda is a ? 1 ? and the data sampled on the sda pin is ? 0 ?, then a bus collision has taken place. the master will set the bus collision interrupt flag, bcl1if, and reset the i 2 c port to its idle state ( figure 25-32 ). if a transmit was in progress when the bus collision occurred, the transmission is halted, the bf flag is cleared, the sda and scl lines are deasserted and the ssp1buf can be written to. when the user services the bus collision interrupt service routine and if the i 2 c bus is free, the user can resume communication by asserting a start condition. if a start, repeated start, stop or acknowledge condi- tion was in progress when the bus collision occurred, the condition is aborted, the sda and scl lines are deas- serted and the respective control bits in the ssp1con2 register are cleared. when the user services the bus col- lision interrupt service routine and if the i 2 c bus is free, the user can resume communication by asserting a start condition. the master will continue to monitor the sda and scl pins. if a stop condition occurs, the ssp1if bit will be set. a write to the ssp1buf will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. in multi-master mode, the interrupt generation on the detection of start and stop conditions allows the deter- mination of when the bus is free. control of the i 2 c bus can be taken when the p bit is set in the ssp1stat register, or the bus is idle and the s and p bits are cleared. scl sda sda asserted low before rising edge of clock write to ssp1con2, set pen falling edge of scl = 1 for t brg , followed by sda = 1 for t brg 9th clock scl brought high after t brg note: t brg = one baud rate generator period. t brg t brg after sda sampled high. p bit (ssp1stat<4>) is set. t brg to setup stop condition ack p t brg pen bit (ssp1con2<2>) is cleared by hardware and the ssp1if bit is set
? 2011-2012 microchip technology inc. ds41441c-page 243 pic12(l)f1840 figure 25-32: bus collision timing for transmit and acknowledge sda scl bcl1if sda released sda line pulled low by another source sample sda. while scl is high, data does not match what is driven bus collision has occurred. set bus collision interrupt (bcl1if) by the master. by master data changes while scl = 0
pic12(l)f1840 ds41441c-page 244 ? 2011-2012 microchip technology inc. 25.6.13.1 bus collision during a start condition during a start condition, a bus collision occurs if: a) sda or scl are sampled low at the beginning of the start condition ( figure 25-33 ). b) scl is sampled low before sda is asserted low ( figure 25-34 ). during a start condition, both the sda and the scl pins are monitored. if the sda pin is already low, or the scl pin is already low, then all of the following occur: ? the start condition is aborted, ? the bcl1if flag is set and ? the mssp1 module is reset to its idle state ( figure 25-33 ). the start condition begins with the sda and scl pins deasserted. when the sda pin is sampled high, the baud rate generator is loaded and counts down. if the scl pin is sampled low while sda is high, a bus colli- sion occurs because it is assumed that another master is attempting to drive a data ? 1 ? during the start condition. if the sda pin is sampled low during this count, the brg is reset and the sda line is asserted early ( figure 25-35 ). if, however, a ? 1 ? is sampled on the sda pin, the sda pin is asserted low at the end of the brg count. the baud rate generator is then reloaded and counts down to zero; if the scl pin is sampled as ? 0 ? during this time, a bus collision does not occur. at the end of the brg count, the scl pin is asserted low. figure 25-33: bus collision during start condition (sda only) note: the reason that bus collision is not a fac- tor during a start condition is that no two bus masters can assert a start condition at the exact same time. therefore, one master will always assert sda before the other. this condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address fol- lowing the start condition. if the address is the same, arbitration must be allowed to continue into the data portion, repeated start or stop conditions. sda scl sen sda sampled low before sda goes low before the sen bit is set. s bit and ssp1if set because ssp1 module reset into idle state. sen cleared automatically because of bus collision. s bit and ssp1if set because set sen, enable start condition if sda = 1 , scl = 1 sda = 0 , scl = 1 . bcl1if s ssp1if sda = 0 , scl = 1 . ssp1if and bcl1if are cleared by software ssp1if and bcl1if are cleared by software set bcl1if, start condition. set bcl1if.
? 2011-2012 microchip technology inc. ds41441c-page 245 pic12(l)f1840 figure 25-34: bus collision d uring start condition (scl = 0 ) figure 25-35: brg reset due to sda arbitration during start condition sda scl sen bus collision occurs. set bcl1if. scl = 0 before sda = 0 , set sen, enable start sequence if sda = 1 , scl = 1 t brg t brg sda = 0 , scl = 1 bcl1if s ssp1if interrupt cleared by software bus collision occurs. set bcl1if. scl = 0 before brg time-out, ? 0 ?? 0 ? ? 0 ? ? 0 ? sda scl sen set s less than t brg t brg sda = 0 , scl = 1 bcl1if s ssp1if s interrupts cleared by software set ssp1if sda = 0 , scl = 1 , scl pulled low after brg time-out set ssp1if ? 0 ? sda pulled low by other master. reset brg and assert sda. set sen, enable start sequence if sda = 1 , scl = 1
pic12(l)f1840 ds41441c-page 246 ? 2011-2012 microchip technology inc. 25.6.13.2 bus collision during a repeated start condition during a repeated start condition, a bus collision occurs if: a) a low level is sampled on sda when scl goes from low level to high level (case 1). b) scl goes low before sda is asserted low, indicating that another master is attempting to transmit a data ? 1 ? (case 2). when the user releases sda and the pin is allowed to float high, the brg is loaded with ssp1add and counts down to zero. the scl pin is then deasserted and when sampled high, the sda pin is sampled. if sda is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ? 0 ?, figure 25-36 ). if sda is sampled high, the brg is reloaded and begins counting. if sda goes from high-to-low before the brg times out, no bus collision occurs because no two masters can assert sda at exactly the same time. if scl goes from high-to-low before the brg times out and sda has not already been asserted, a bus collision occurs. in this case, another master is attempting to transmit a data ? 1 ? during the repeated start condition, see figure 25-37 . if, at the end of the brg time-out, both scl and sda are still high, the sda pin is driven low and the brg is reloaded and begins counting. at the end of the count, regardless of the status of the scl pin, the scl pin is driven low and the repeated start condition is complete. figure 25-36: bus collision during a repeat ed start condition (case 1) figure 25-37: bus collision during repeat ed start condition (case 2) sda scl rsen bcl1if s ssp1if sample sda when scl goes high. if sda = 0 , set bcl1if and release sda and scl. cleared by software ? 0 ? ? 0 ? sda scl bcl1if rsen s ssp1if interrupt cleared by software scl goes low before sda, set bcl1if. release sda and scl. t brg t brg ? 0 ?
? 2011-2012 microchip technology inc. ds41441c-page 247 pic12(l)f1840 25.6.13.3 bus collision during a stop condition bus collision occurs during a stop condition if: a) after the sda pin has been deasserted and allowed to float high, sda is sampled low after the brg has timed out (case 1). b) after the scl pin is deasserted, scl is sampled low before sda goes high (case 2). the stop condition begins with sda asserted low. when sda is sampled low, the scl pin is allowed to float. when the pin is sampled high (clock arbitration), the baud rate generator is loaded with ssp1add and counts down to 0. after the brg times out, sda is sampled. if sda is sampled low, a bus collision has occurred. this is due to another master attempting to drive a data ? 0 ? ( figure 25-38 ). if the scl pin is sampled low before sda is allowed to float high, a bus collision occurs. this is another case of another master attempting to drive a data ? 0 ? ( figure 25-39 ). figure 25-38: bus collision during a stop condition (case 1) figure 25-39: bus collision during a stop condition (case 2) sda scl bcl1if pen p ssp1if t brg t brg t brg sda asserted low sda sampled low after t brg , set bcl1if ? 0 ? ? 0 ? sda scl bcl1if pen p ssp1if t brg t brg t brg assert sda scl goes low before sda goes high, set bcl1if ? 0 ? ? 0 ?
pic12(l)f1840 ds41441c-page 248 ? 2011-2012 microchip technology inc. table 25-3: summary of registers associated with i 2 c? operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie peie tmr0ie inte iocie tmr0if intf iocif 74 pie1 tmr1gie adie rcie txie ssp1ie ccp1ie tmr2ie tmr1ie 75 pie2 osfie ? c1ie eeie bcl1ie ? ? ? 76 pir1 tmr1gif adif rcif txif ssp1if ccp1if tmr2if tmr1if 77 pir2 osfif ? c1if eeif bcl1if ? ? ? 78 ssp1add add<7:0> 255 ssp1buf synchronous serial port receive buffer/transmit register 205 * ssp1con1 wcol sspov sspen ckp sspm<3:0> 252 ssp1con2 gcen ackstat ackdt acken rcen pen rsen sen 253 ssp1con3 acktim pcie scie boen sdaht sbcde ahen dhen 254 ssp1msk msk<7:0> 255 ssp1stat smp cke d/a p s r/w ua bf 250 trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 105 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by the mssp module in i 2 c? mode. * page provides register information.
? 2011-2012 microchip technology inc. ds41441c-page 249 pic12(l)f1840 25.7 baud rate generator the mssp1 module has a baud rate generator avail- able for clock generation in both i 2 c and spi master modes. the baud rate generator (brg) reload value is placed in the ssp1add register ( register 25-6 ). when a write occurs to ssp1buf, the baud rate gen- erator will automatically begin counting down. once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. an internal signal ?reload? in figure 25-40 triggers the value from ssp1add to be loaded into the brg counter. this occurs twice for each oscillation of the module clock line. the logic dictating when the reload signal is asserted depends on the mode the mssp1 is being operated in. table 25-4 demonstrates clock rates based on instruction cycles and the brg value loaded into ssp1add. equation 25-1: figure 25-40: baud rate genera tor block diagram table 25-4: mssp1 clock rate w/brg f clock f osc sspxadd 1 + ?? 4 ?? ------------------------------------------------- = note: values of 0x00, 0x01 and 0x02 are not valid for ssp1add when used as a baud rate generator for i 2 c. this is an implementation limitation. f osc f cy brg value f clock (2 rollovers of brg) 32 mhz 8 mhz 13h 400 khz (1) 32 mhz 8 mhz 19h 308 khz 32 mhz 8 mhz 4fh 100 khz 16 mhz 4 mhz 09h 400 khz (1) 16 mhz 4 mhz 0ch 308 khz 16 mhz 4 mhz 27h 100 khz 4 mhz 1 mhz 09h 100 khz note 1: the i 2 c interface does not conform to the 400 khz i 2 c specification (which applies to rates greater than 100 khz) in all details, but may be used with care where higher rates are required by the application. ssp1m<3:0> brg down counter ssp1clk f osc /2 ssp1add<7:0> ssp1m<3:0> scl reload control reload
pic12(l)f1840 ds41441c-page 250 ? 2011-2012 microchip technology inc. 25.8 register definitions: mssp control register 25-1: sspstat: ssp status register r/w-0/0 r/w-0/0 r-0/0 r-0/0 r-0/0 r-0/0 r-0/0 r-0/0 smp cke d/a psr/w ua bf bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 smp: spi data input sample bit spi master mode: 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time spi slave mode: smp must be cleared when spi is used in slave mode in i 2 c master or slave mode: 1 = slew rate control disabled for standard speed mode (100 khz and 1 mhz) 0 = slew rate control enabled for high speed mode (400 khz) bit 6 cke: spi clock edge select bit (spi mode only) in spi master or slave mode: 1 = transmit occurs on transition from active to idle clock state 0 = transmit occurs on transition from idle to active clock state in i 2 c ? mode only: 1 = enable input logic so that thresholds are compliant with smbus specification 0 = disable smbus specific inputs bit 5 d/a : data/address bit (i 2 c mode only) 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4 p: stop bit (i 2 c mode only. this bit is cleared when the ms sp module is disabled, sspen is cleared.) 1 = indicates that a stop bit has been detected last (this bit is ? 0 ? on reset) 0 = stop bit was not detected last bit 3 s: start bit (i 2 c mode only. this bit is cleared when the ms sp module is disabled, sspen is cleared.) 1 = indicates that a start bit has been detected last (this bit is ? 0 ? on reset) 0 = start bit was not detected last bit 2 r/w : read/write bit information (i 2 c mode only) this bit holds the r/w bit information following the last address match. this bit is only valid from the address match to the next start bit, stop bit, or not ack bit. in i 2 c slave mode: 1 = read 0 = write in i 2 c master mode: 1 = transmit is in progress 0 = transmit is not in progress or-ing this bit with sen, rsen, pen, rcen or acken will indicate if the mssp is in idle mode. bit 1 ua: update address bit (10-bit i 2 c mode only) 1 = indicates that the user needs to update the address in the sspadd register 0 = address does not need to be updated
? 2011-2012 microchip technology inc. ds41441c-page 251 pic12(l)f1840 bit 0 bf: buffer full status bit receive (spi and i 2 c modes): 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty transmit (i 2 c mode only): 1 = data transmit in progress (does not include the ack and stop bits), sspbuf is full 0 = data transmit complete (does not include the ack and stop bits), sspbuf is empty register 25-1: sspstat: ssp status register (continued)
pic12(l)f1840 ds41441c-page 252 ? 2011-2012 microchip technology inc. register 25-2: ssp1con1: ss p1 control register 1 r/c/hs-0/0 r/c/hs-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 wcol ssp1ov ssp1en ckp ssp1m<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared hs = bit is set by hardware c = user cleared bit 7 wcol: write collision detect bit master mode: 1 = a write to the ssp1buf register was attempted while the i 2 c conditions were not valid for a transmission to be started 0 = no collision slave mode: 1 = the ssp1buf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision bit 6 ssp1ov: receive overflow indicator bit (1) in spi mode: 1 = a new byte is received while the ssp1buf register is still holding the previous data. in case of overflow, the data in ssp1sr is lost. overflow can only occur in slave mode. in slave mode, the user must read the ssp1buf, even if only transmitting data, to avoid setting overflow. in master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the ssp1buf register (must be cleared in software). 0 = no overflow in i 2 c mode: 1 = a byte is received while the ssp1buf register is still holding the previous byte. ssp1ov is a ?don?t care? in transmit mode (must be cleared in software). 0 = no overflow bit 5 ssp1en: synchronous serial port enable bit in both modes, when enabled, these pins must be properly configured as input or output in spi mode: 1 = enables serial port and configures sck, sdo, sdi and ss as the source of the serial port pins (2) 0 = disables serial port and configures these pins as i/o port pins in i 2 c mode: 1 = enables the serial port and configures the sda and scl pins as the source of the serial port pins (3) 0 = disables serial port and configures these pins as i/o port pins bit 4 ckp: clock polarity select bit in spi mode: 1 = idle state for clock is a high level 0 = idle state for clock is a low level in i 2 c slave mode: scl release control 1 = enable clock 0 = holds clock low (clock stretch). (used to ensure data setup time.) in i 2 c master mode: unused in this mode bit 3-0 sspm<3:0>: synchronous serial port mode select bits 1111 = i 2 c slave mode, 10-bit address with start and stop bit interrupts enabled 1110 = i 2 c slave mode, 7-bit address with start and stop bit interrupts enabled 1101 = reserved 1100 = reserved 1011 = i 2 c firmware controlled master mode (slave idle) 1010 = spi master mode, clock = f osc /(4 * (sspadd+1)) (5) 1001 = reserved 1000 = i 2 c master mode, clock = f osc / (4 * (sspadd+1)) (4) 0111 = i 2 c slave mode, 10-bit address 0110 = i 2 c slave mode, 7-bit address 0101 = spi slave mode, clock = sck pin, ss pin control disabled, ss can be used as i/o pin 0100 = spi slave mode, clock = sck pin, ss pin control enabled 0011 = spi master mode, clock = tmr2 output/2 0010 = spi master mode, clock = f osc /64 0001 = spi master mode, clock = f osc /16 0000 = spi master mode, clock = f osc /4 note 1: in master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the ssp1buf register. 2: when enabled, these pins must be properly configured as input or output. 3: when enabled, the sda and scl pins must be configured as inputs. 4: ssp1add values of 0, 1 or 2 are not supported for i 2 c mode. 5: ssp1add value of ? 0 ? is not supported. use ssp1m = 0000 instead.
? 2011-2012 microchip technology inc. ds41441c-page 253 pic12(l)f1840 register 25-3: ssp1con2: ss p1 control register 2 r/w-0/0 r-0/0 r/w-0/0 r/s/hs-0/0 r/s/hs- 0/0 r/s/hs-0/0 r/s/hs-0/0 r/w/hs-0/0 gcen ackstat ackdt acken rcen pen rsen sen bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared hc = cleared by hardware s = user set bit 7 gcen: general call enable bit (in i 2 c slave mode only) 1 = enable interrupt when a general call address (0x00 or 00h) is received in the ssp1sr 0 = general call address disabled bit 6 ackstat: acknowledge status bit (in i 2 c mode only) 1 = acknowledge was not received 0 = acknowledge was received bit 5 ackdt: acknowledge data bit (in i 2 c mode only) in receive mode: value transmitted when the user initiates an acknowledge sequence at the end of a receive 1 = not acknowledge 0 = acknowledge bit 4 acken: acknowledge sequence enable bit (in i 2 c master mode only) in master receive mode: 1 = initiate acknowledge sequence on sda and scl pins, and transmit ackdt data bit. automatically cleared by hardware. 0 = acknowledge sequence idle bit 3 rcen: receive enable bit (in i 2 c master mode only) 1 = enables receive mode for i 2 c 0 = receive idle bit 2 pen: stop condition enable bit (in i 2 c master mode only) sckmssp r elease control: 1 = initiate stop condition on sda and scl pins. automatically cleared by hardware. 0 = stop condition idle bit 1 rsen: repeated start condition enable bit (in i 2 c master mode only) 1 = initiate repeated start condition on sda and scl pins. automatically cleared by hardware. 0 = repeated start condition idle bit 0 sen: start condition enable/stretch enable bit i n master mode: 1 = initiate start condition on sda and scl pins. automatically cleared by hardware. 0 = start condition idle in slave mode: 1 = clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = clock stretching is disabled note 1: for bits acken, rcen, pen, rsen, sen: if the i 2 c module is not in the idle mode, this bit may not be set (no spooling) and the ssp1buf may not be written (or writes to the ssp1buf are disabled).
pic12(l)f1840 ds41441c-page 254 ? 2011-2012 microchip technology inc. register 25-4: ssp1con3: ss p1 control register 3 r-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 acktim pcie scie boen sdaht sbcde ahen dhen bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 acktim: acknowledge time status bit (i 2 c mode only) (3) 1 = indicates the i 2 c bus is in an acknowledge sequence, set on 8 th falling edge of scl clock 0 = not an acknowledge sequence, cleared on 9 th rising edge of scl clock bit 6 pcie : stop condition interrupt enable bit (i 2 c mode only) 1 = enable interrupt on detection of stop condition 0 = stop detection interrupts are disabled (2) bit 5 scie : start condition interrupt enable bit (i 2 c mode only) 1 = enable interrupt on detection of start or restart conditions 0 = start detection interrupts are disabled (2) bit 4 boen: buffer overwrite enable bit in spi slave mode: (1) 1 = ssp1buf updates every time that a new data byte is shifted in ignoring the bf bit 0 = if new byte is received with bf bit of the ssp1stat register already set, ssp1ov bit of the ssp1con1 register is set, and the buffer is not updated in i 2 c master mode and spi master mode: this bit is ignored. in i 2 c slave mode: 1 = ssp1buf is updated and ack is generated for a received address/data byte, ignoring the state of the ssp1ov bit only if the bf bit = 0 . 0 = ssp1buf is only updated when ssp1ov is clear bit 3 sdaht: sda hold time selection bit (i 2 c mode only) 1 = minimum of 300 ns hold time on sda after the falling edge of scl 0 = minimum of 100 ns hold time on sda after the falling edge of scl bit 2 sbcde: slave mode bus collision detect enable bit (i 2 c slave mode only) if on the rising edge of scl, sda is sampled low when the module is outputting a high state, the bcl1if bit of the pir2 register is set, and bus goes idle 1 = enable slave bus collision interrupts 0 = slave bus collision interrupts are disabled bit 1 ahen: address hold enable bit (i 2 c slave mode only) 1 = following the 8th falling edge of scl for a matching received address byte; ckp bit of the ssp1con1 register will be cleared and the scl will be held low. 0 = address holding is disabled bit 0 dhen: data hold enable bit (i 2 c slave mode only) 1 = following the 8th falling edge of scl for a received data byte; slave hardware clears the ckp bit of the ssp1con1 register and scl is held low. 0 = data holding is disabled note 1: for daisy-chained spi operation; allows the user to ignore all but the last received byte. ssp1ov is still set when a new byte is received and bf = 1 , but hardware continues to write the most recent byte to ssp1buf. 2: this bit has no effect in slave modes that start and stop condition detection is explicitly listed as enabled. 3: the acktim status bit is only active when the ahen bit or dhen bit is set.
? 2011-2012 microchip technology inc. ds41441c-page 255 pic12(l)f1840 register 25-5: ssp1msk: ssp1 mask register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 msk<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-1 msk<7:1>: mask bits 1 = the received address bit n is compared to ssp1add to detect i 2 c address match 0 = the received address bit n is not used to detect i 2 c address match bit 0 msk<0>: mask bit for i 2 c slave mode, 10-bit address i 2 c slave mode, 10-bit address (ssp1m<3:0> = 0111 or 1111 ): 1 = the received address bit 0 is compared to ssp1add<0> to detect i 2 c address match 0 = the received address bit 0 is not used to detect i 2 c address match i 2 c slave mode, 7-bit address, the bit is ignored register 25-6: ssp1add: mssp1 address and baud rate register (i 2 c mode) r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 add<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared master mode: bit 7-0 add<7:0>: baud rate clock divider bits scl pin clock period = ((add<7:0> + 1) *4)/f osc 10-bit slave mode ? most significant address by te: bit 7-3 not used: unused for most significant address byte. bit state of this register is a ?don?t care?. bit pat- tern sent by master is fixed by i 2 c specification and must be equal to ? 11110 ?. however, those bits are compared by hardware and are not affected by the value in this register. bit 2-1 add<2:1>: two most significant bits of 10-bit address bit 0 not used: unused in this mode. bit state is a ?don?t care.? 10-bit slave mode ? least significant address by te: bit 7-0 add<7:0>: eight least significant bits of 10-bit address 7-bit slave mode: bit 7-1 add<7:1>: 7-bit address bit 0 not used: unused in this mode. bit state is a ?don?t care.?
pic12(l)f1840 ds41441c-page 256 ? 2011-2012 microchip technology inc. notes:
? 2011-2012 microchip technology inc. ds41441c-page 257 pic12(l)f1840 26.0 enhanced universal synchronous asynchronous receiver transmitter (eusart) the enhanced universal synchronous asynchronous receiver transmitter (eusart) module is a serial i/o communications peripheral. it contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution. the eusart, also known as a serial communications interface (sci), can be configured as a full-duplex asynchronous system or half-duplex synchronous system. full-duplex mode is useful for communications with peripheral systems, such as crt terminals and personal computers. half-duplex synchronous mode is intended for communications with peripheral devices, such as a/d or d/a integrated circuits, serial eeproms or other microcontrollers. these devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a master synchronous device. the eusart module includes the following capabilities: ? full-duplex asynchronous transmit and receive ? two-character input buffer ? one-character output buffer ? programmable 8-bit or 9-bit character length ? address detection in 9-bit mode ? input buffer overrun error detection ? received character framing error detection ? half-duplex synchronous master ? half-duplex synchronous slave ? programmable clock polarity in synchronous modes ? sleep operation the eusart module implements the following additional features, making it ideally suited for use in local interconnect network (lin) bus systems: ? automatic detection and calibration of the baud rate ? wake-up on break reception ? 13-bit break character transmit block diagrams of the eusart transmitter and receiver are shown in figure 26-1 and figure 26-2 . figure 26-1: eusart transmi t block diagram txif txie interrupt txen tx9d msb lsb data bus txreg register transmit shift register (tsr) (8) 0 tx9 trmt spen tx/ck pin pin buffer and control 8 spbrgl spbrgh brg16 f osc n n + 1 multiplier x4 x16 x64 sync 1x00 0 brgh x110 0 brg16 x101 0 baud rate generator ???
pic12(l)f1840 ds41441c-page 258 ? 2011-2012 microchip technology inc. figure 26-2: eusart receiv e block diagram the operation of the eusart module is controlled through three registers: ? transmit status and control (txsta) ? receive status and control (rcsta) ? baud rate control (baudcon) these registers are detailed in register 26-1 , register 26-2 and register 26-3 , respectively. when the receiver or transmitter section is not enabled then the corresponding rx or tx pin may be used for general purpose input and output. rx/dt pin pin buffer and control spen data recovery cren oerr ferr rsr register msb lsb rx9d rcreg register fifo interrupt rcif rcie data bus 8 stop start (8) 7 1 0 rx9 ? ? ? spbrgl spbrgh brg16 rcidl f osc n n + 1 multiplier x4 x16 x64 sync 1x00 0 brgh x110 0 brg16 x101 0 baud rate generator
? 2011-2012 microchip technology inc. ds41441c-page 259 pic12(l)f1840 26.1 eusart asynchronous mode the eusart transmits and receives data using the standard non-return-to-zero (nrz) format. nrz is implemented with two levels: a v oh mark state which represents a ? 1 ? data bit, and a v ol space state which represents a ? 0 ? data bit. nrz refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission. an nrz transmission port idles in the mark state. each character transmission consists of one start bit followed by eight or nine data bits and is always terminated by one or more stop bits. the start bit is always a space and the stop bits are always marks. the most common data format is 8 bits. each transmitted bit persists for a period of 1/(baud rate). an on-chip dedicated 8-bit/16-bit baud rate generator is used to derive standard baud rate frequencies from the system oscillator. see tab l e 2 6- 5 for examples of baud rate configurations. the eusart transmits and receives the lsb first. the eusart?s transmitter and receiver are functionally independent, but share the same data format and baud rate. parity is not supported by the hardware, but can be implemented in software and stored as the ninth data bit. 26.1.1 eusart asynchronous transmitter the eusart transmitter block diagram is shown in figure 26-1 . the heart of the transmitter is the serial transmit shift register (tsr), which is not directly accessible by software. the tsr obtains its data from the transmit buffer, which is the txreg register. 26.1.1.1 enabling the transmitter the eusart transmitter is enabled for asynchronous operations by configuring the following three control bits: ?txen = 1 ? sync = 0 ? spen = 1 all other eusart control bits are assumed to be in their default state. setting the txen bit of the txsta register enables the transmitter circuitry of the eusart. clearing the sync bit of the txsta register configures the eusart for asynchronous operation. setting the spen bit of the rcsta register enables the eusart and automatically configures the tx/ck i/o pin as an output. if the tx/ck pin is shared with an analog peripheral, the analog i/o function must be disabled by clearing the corresponding ansel bit. 26.1.1.2 transmitting data a transmission is initiated by writing a character to the txreg register. if this is the first character, or the previous character has been completely flushed from the tsr, the data in the txreg is immediately transferred to the tsr register. if the tsr still contains all or part of a previous character, the new character data is held in the txreg until the stop bit of the previous character has been transmitted. the pending character in the txreg is then transferred to the tsr in one t cy immediately following the stop bit transmission. the transmission of the start bit, data bits and stop bit sequence commences immediately following the transfer of the data to the tsr from the txreg. 26.1.1.3 transmit data polarity the polarity of the transmit data can be controlled with the sckp bit of the baudcon register. the default state of this bit is ? 0 ? which selects high true transmit idle and data bits. setting the sckp bit to ? 1 ? will invert the transmit data resulting in low true idle and data bits. the sckp bit controls transmit data polarity in asynchronous mode only. in synchronous mode, the sckp bit has a different function. see section 26.5.1.2 ?clock polarity? . 26.1.1.4 transmit interrupt flag the txif interrupt flag bit of the pir1 register is set whenever the eusart transmitter is enabled and no character is being held for transmission in the txreg. in other words, the txif bit is only clear when the tsr is busy with a character and a new character has been queued for transmission in the txreg. the txif flag bit is not cleared immediately upon writing txreg. txif becomes valid in the second instruction cycle following the write execution. polling txif immediately following the txreg write will return invalid results. the txif bit is read-only, it cannot be set or cleared by software. the txif interrupt can be enabled by setting the txie interrupt enable bit of the pie1 register. however, the txif flag bit will be set whenever the txreg is empty, regardless of the state of txie enable bit. to use interrupts when transmitting data, set the txie bit only when there is more data to send. clear the txie interrupt enable bit upon writing the last character of the transmission to the txreg. note 1: the txif transmitter interrupt flag is set when the txen enable bit is set.
pic12(l)f1840 ds41441c-page 260 ? 2011-2012 microchip technology inc. 26.1.1.5 tsr status the trmt bit of the txsta register indicates the status of the tsr register. this is a read-only bit. the trmt bit is set when the tsr register is empty and is cleared when a character is transferred to the tsr register from the txreg. the trmt bit remains clear until all bits have been shifted out of the tsr register. no interrupt logic is tied to this bit, so the user has to poll this bit to determine the tsr status. 26.1.1.6 transmitting 9-bit characters the eusart supports 9-bit character transmissions. when the tx9 bit of the txsta register is set, the eusart will shift 9 bits out for each character transmit- ted. the tx9d bit of the txsta register is the ninth, and most significant, data bit. when transmitting 9-bit data, the tx9d data bit must be written before writing the 8 least significant bits into the txreg. all nine bits of data will be transferred to the tsr shift register immediately after the txreg is written. a special 9-bit address mode is available for use with multiple receivers. see section 26.1.2.7 ?address detection? for more information on the address mode. 26.1.1.7 asynchronous transmission set-up: 1. initialize the spbrgh, spbrgl register pair and the brgh and brg16 bits to achieve the desired baud rate (see section 26.4 ?eusart baud rate generator (brg)? ). 2. enable the asynchronous serial port by clearing the sync bit and setting the spen bit. 3. if 9-bit transmission is desired, set the tx9 control bit. a set ninth data bit will indicate that the 8 least significant data bits are an address when the receiver is set for address detection. 4. set sckp bit if inverted transmit is desired. 5. enable the transmission by setting the txen control bit. this will cause the txif interrupt bit to be set. 6. if interrupts are desired, set the txie interrupt enable bit of the pie1 register. an interrupt will occur immediately provided that the gie and peie bits of the intcon register are also set. 7. if 9-bit transmission is selected, the ninth bit should be loaded into the tx9d data bit. 8. load 8-bit data into the txreg register. this will start the transmission. figure 26-3: asynchronous transmission figure 26-4: asynchronous transmiss ion (back-to-back) note: the tsr register is not mapped in data memory, so it is not available to the user. word 1 stop bit word 1 transmit shift reg. start bit bit 0 bit 1 bit 7/8 write to txreg word 1 brg output (shift clock) tx/ck txif bit (transmit buffer reg. empty flag) trmt bit (transmit shift reg. empty flag) 1 t cy pin transmit shift reg. write to txreg brg output (shift clock) tx/ck trmt bit (transmit shift reg. empty flag) word 1 word 2 word 1 word 2 start bit stop bit start bit transmit shift reg. word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows two consecutive transmissions. 1 t cy 1 t cy pin txif bit (transmit buffer reg. empty flag)
? 2011-2012 microchip technology inc. ds41441c-page 261 pic12(l)f1840 table 26-1: summary of registers asso ciated with asynchronous transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baudcon abdovf rcidl ? sckp brg16 ? wue abden 269 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 74 pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 75 pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 77 rcsta spen rx9 sren cren adden ferr oerr rx9d 268 spbrgl brg<7:0> 270 * spbrgh brg<15:8> 270 * txreg eusart transmit data register 259 * txsta csrc tx9 txen sync sendb brgh trmt tx9d 267 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used for asynchronous transmission. * page provides register information.
pic12(l)f1840 ds41441c-page 262 ? 2011-2012 microchip technology inc. 26.1.2 eusart asynchronous receiver the asynchronous mode is typically used in rs-232 systems. the receiver block diagram is shown in figure 26-2 . the data is received on the rx/dt pin and drives the data recovery block. the data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial receive shift register (rsr) operates at the bit rate. when all 8 or 9 bits of the character have been shifted in, they are immediately transferred to a two character first-in-first-out (fifo) memory. the fifo buffering allows reception of two complete characters and the start of a third character before software must start servicing the eusart receiver. the fifo and rsr registers are not directly accessible by software. access to the received data is via the rcreg register. 26.1.2.1 enabling the receiver the eusart receiver is enabled for asynchronous operation by configuring the following three control bits: ? cren = 1 ? sync = 0 ? spen = 1 all other eusart control bits are assumed to be in their default state. setting the cren bit of the rcsta register enables the receiver circuitry of the eusart. clearing the sync bit of the txsta register configures the eusart for asynchronous operation. setting the spen bit of the rcsta register enables the eusart. the programmer must set the corresponding tris bit to configure the rx/dt i/o pin as an input. 26.1.2.2 receiving data the receiver data recovery circuit initiates character reception on the falling edge of the first bit. the first bit, also known as the start bit, is always a zero. the data recovery circuit counts one-half bit time to the center of the start bit and verifies that the bit is still a zero. if it is not a zero then the data recovery circuit aborts character reception, without generating an error, and resumes looking for the falling edge of the start bit. if the start bit zero verification succeeds then the data recovery circuit counts a full bit time to the center of the next bit. the bit is then sampled by a majority detect circuit and the resulting ? 0 ? or ? 1 ? is shifted into the rsr. this repeats until all data bits have been sampled and shifted into the rsr. one final bit time is measured and the level sampled. this is the stop bit, which is always a ? 1 ?. if the data recovery circuit samples a ? 0 ? in the stop bit position then a framing error is set for this character, otherwise the framing error is cleared for this character. see section 26.1.2.4 ?receive framing error? for more information on framing errors. immediately after all data bits and the stop bit have been received, the character in the rsr is transferred to the eusart receive fifo and the rcif interrupt flag bit of the pir1 register is set. the top character in the fifo is transferred out of the fifo by reading the rcreg register. 26.1.2.3 receive interrupts the rcif interrupt flag bit of the pir1 register is set whenever the eusart receiver is enabled and there is an unread character in the receive fifo. the rcif interrupt flag bit is read-only, it cannot be set or cleared by software. rcif interrupts are enabled by setting all of the following bits: ? rcie, interrupt enable bit of the pie1 register ? peie, peripheral interrupt enable bit of the intcon register ? gie, global interrupt enable bit of the intcon register the rcif interrupt flag bit will be set when there is an unread character in the fifo, regardless of the state of interrupt enable bits. note 1: if the rx/dt function is on an analog pin, the corresponding ansel bit must be cleared for the receiver to function. note: if the receive fifo is overrun, no additional characters will be received until the overrun condition is cleared. see section 26.1.2.5 ?receive overrun error? for more information on overrun errors.
? 2011-2012 microchip technology inc. ds41441c-page 263 pic12(l)f1840 26.1.2.4 receive framing error each character in the receive fifo buffer has a corresponding framing error status bit. a framing error indicates that a stop bit was not seen at the expected time. the framing error status is accessed via the ferr bit of the rcsta register. the ferr bit represents the status of the top unread character in the receive fifo. therefore, the ferr bit must be read before reading the rcreg. the ferr bit is read-only and only applies to the top unread character in the receive fifo. a framing error (ferr = 1 ) does not preclude reception of additional characters. it is not necessary to clear the ferr bit. reading the next character from the fifo buffer will advance the fifo to the next character and the next corresponding framing error. the ferr bit can be forced clear by clearing the spen bit of the rcsta register which resets the eusart. clearing the cren bit of the rcsta register does not affect the ferr bit. a framing error by itself does not generate an interrupt. 26.1.2.5 receive overrun error the receive fifo buffer can hold two characters. an overrun error will be generated if a third character, in its entirety, is received before the fifo is accessed. when this happens the oerr bit of the rcsta register is set. the characters already in the fifo buffer can be read but no additional characters will be received until the error is cleared. the error must be cleared by either clearing the cren bit of the rcsta register or by resetting the eusart by clearing the spen bit of the rcsta register. 26.1.2.6 receiving 9-bit characters the eusart supports 9-bit character reception. when the rx9 bit of the rcsta register is set the eusart will shift 9 bits into the rsr for each character received. the rx9d bit of the rcsta register is the ninth and most significant data bit of the top unread character in the receive fifo. when reading 9-bit data from the receive fifo buffer, the rx9d data bit must be read before reading the 8 least significant bits from the rcreg. 26.1.2.7 address detection a special address detection mode is available for use when multiple receivers share the same transmission line, such as in rs-485 systems. address detection is enabled by setting the adden bit of the rcsta register. address detection requires 9-bit character reception. when address detection is enabled, only characters with the ninth data bit set will be transferred to the receive fifo buffer, thereby setting the rcif interrupt bit. all other characters will be ignored. upon receiving an address character, user software determines if the address matches its own. upon address match, user software must disable address detection by clearing the adden bit before the next stop bit occurs. when user software detects the end of the message, determined by the message protocol used, software places the receiver back into the address detection mode by setting the adden bit. note: if all receive characters in the receive fifo have framing errors, repeated reads of the rcreg will not clear the ferr bit.
pic12(l)f1840 ds41441c-page 264 ? 2011-2012 microchip technology inc. 26.1.2.8 asynchronous reception set-up: 1. initialize the spbrgh, spbrgl register pair and the brgh and brg16 bits to achieve the desired baud rate (see section 26.4 ?eusart baud rate generator (brg)? ). 2. clear the ansel bit for the rx pin (if applicable). 3. enable the serial port by setting the spen bit. the sync bit must be clear for asynchronous operation. 4. if interrupts are desired, set the rcie bit of the pie1 register and the gie and peie bits of the intcon register. 5. if 9-bit reception is desired, set the rx9 bit. 6. enable reception by setting the cren bit. 7. the rcif interrupt flag bit will be set when a character is transferred from the rsr to the receive buffer. an interrupt will be generated if the rcie interrupt enable bit was also set. 8. read the rcsta register to get the error flags and, if 9-bit data reception is enabled, the ninth data bit. 9. get the received 8 least significant data bits from the receive buffer by reading the rcreg register. 10. if an overrun occurred, clear the oerr flag by clearing the cren receiver enable bit. 26.1.2.9 9-bit address detection mode set-up this mode would typically be used in rs-485 systems. to set up an asynchronous reception with address detect enable: 1. initialize the spbrgh, spbrgl register pair and the brgh and brg16 bits to achieve the desired baud rate (see section 26.4 ?eusart baud rate generator (brg)? ). 2. clear the ansel bit for the rx pin (if applicable). 3. enable the serial port by setting the spen bit. the sync bit must be clear for asynchronous operation. 4. if interrupts are desired, set the rcie bit of the pie1 register and the gie and peie bits of the intcon register. 5. enable 9-bit reception by setting the rx9 bit. 6. enable address detection by setting the adden bit. 7. enable reception by setting the cren bit. 8. the rcif interrupt flag bit will be set when a character with the ninth bit set is transferred from the rsr to the receive buffer. an interrupt will be generated if the rcie interrupt enable bit was also set. 9. read the rcsta register to get the error flags. the ninth data bit will always be set. 10. get the received 8 least significant data bits from the receive buffer by reading the rcreg register. software determines if this is the device?s address. 11. if an overrun occurred, clear the oerr flag by clearing the cren receiver enable bit. 12. if the device has been addressed, clear the adden bit to allow all received data into the receive buffer and generate interrupts. figure 26-5: asynchronous reception start bit bit 7/8 bit 1 bit 0 bit 7/8 bit 0 stop bit start bit start bit bit 7/8 stop bit rx/dt pin reg rcv buffer reg. rcv shift read rcv buffer reg. rcreg rcif (interrupt flag) oerr bit cren word 1 rcreg word 2 rcreg stop bit note: this timing diagram shows three words appearing on the rx in put. the rcreg (receive buffer) is read after the third word, causing the oerr (overrun) bit to be set. rcidl
? 2011-2012 microchip technology inc. ds41441c-page 265 pic12(l)f1840 table 26-2: summary of registers asso ciated with asynchronous reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baudcon abdovf rcidl ? sckp brg16 ?wue abden 269 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 74 pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 75 pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 77 rcreg eusart receive data register 262 * rcsta spen rx9 sren cren adden ferr oerr rx9d 268 spbrgl brg<7:0> 270 * spbrgh brg<15:8> 270 * txsta csrc tx9 txen sync sendb brgh trmt tx9d 267 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used for asynchronous reception. * page provides register information.
pic12(l)f1840 ds41441c-page 266 ? 2011-2012 microchip technology inc. 26.2 clock accuracy with asynchronous operation the factory calibrates the internal oscillator block out- put (intosc). however, the intosc frequency may drift as v dd or temperature changes, and this directly affects the asynchronous baud rate. two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. the first (preferred) method uses the osctune register to adjust the intosc output. adjusting the value in the osctune register allows for fine resolution changes to the system clock source. see section 5.2.2 ?internal clock sources? for more information. the other method adjusts the value in the baud rate generator. this can be done automatically with the auto-baud detect feature (see section 26.4.1 ?auto-baud detect? ). there may not be fine enough resolution when adjusting the baud rate generator to compensate for a gradual change in the peripheral clock frequency.
? 2011-2012 microchip technology inc. ds41441c-page 267 pic12(l)f1840 26.3 register definitions: eusart control register 26-1: txsta: transmit status and control register r/w-/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r-1/1 r/w-0/0 csrc tx9 txen (1) sync sendb brgh trmt tx9d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 csrc: clock source select bit asynchronous mode : don?t care synchronous mode : 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) bit 6 tx9: 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5 txen: transmit enable bit (1) 1 = transmit enabled 0 = transmit disabled bit 4 sync: eusart mode select bit 1 = synchronous mode 0 = asynchronous mode bit 3 sendb: send break character bit asynchronous mode : 1 = send sync break on next transmission (cleared by hardware upon completion) 0 = sync break transmission completed synchronous mode : don?t care bit 2 brgh: high baud rate select bit asynchronous mode : 1 = high speed 0 = low speed synchronous mode: unused in this mode bit 1 trmt: transmit shift register status bit 1 = tsr empty 0 = tsr full bit 0 tx9d: ninth bit of transmit data can be address/data bit or a parity bit. note 1: sren/cren overrides txen in sync mode.
pic12(l)f1840 ds41441c-page 268 ? 2011-2012 microchip technology inc. register 26-2: rcsta: receive status and control register (1) r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r-0/0 r-0/0 r-x/x spen rx9 sren cren adden ferr oerr rx9d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 spen: serial port enable bit 1 = serial port enabled (configures rx/dt and tx/ck pins as serial port pins) 0 = serial port disabled (held in reset) bit 6 rx9: 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5 sren: single receive enable bit asynchronous mode : don?t care synchronous mode ? master : 1 = enables single receive 0 = disables single receive this bit is cleared after reception is complete. synchronous mode ? slave don?t care bit 4 cren: continuous receive enable bit asynchronous mode : 1 = enables receiver 0 = disables receiver synchronous mode : 1 = enables continuous receive until enable bit cren is cleared (cren overrides sren) 0 = disables continuous receive bit 3 adden: address detect enable bit asynchronous mode 9-bit (rx9 = 1 ) : 1 = enables address detection, enable interrupt and load the receive buffer when rsr<8> is set 0 = disables address detection, all bytes are received and ninth bit can be used as parity bit asynchronous mode 8-bit (rx9 = 0 ) : don?t care bit 2 ferr: framing error bit 1 = framing error (can be updated by reading rcreg register and receive next valid byte) 0 = no framing error bit 1 oerr: overrun error bit 1 = overrun error (can be cleared by clearing bit cren) 0 = no overrun error bit 0 rx9d: ninth bit of received data this can be address/data bit or a parity bit and must be calculated by user firmware.
? 2011-2012 microchip technology inc. ds41441c-page 269 pic12(l)f1840 register 26-3: baudcon: ba ud rate control register r-0/0 r-1/1 u-0 r/w-0/0 r/w-0/0 u-0 r/w-0/0 r/w-0/0 abdovf rcidl ? sckp brg16 ? wue abden bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 abdovf: auto-baud detect overflow bit asynchronous mode : 1 = auto-baud timer overflowed 0 = auto-baud timer did not overflow synchronous mode : don?t care bit 6 rcidl : receive idle flag bit asynchronous mode : 1 = receiver is idle 0 = start bit has been received and the receiver is receiving synchronous mode : don?t care bit 5 unimplemented: read as ? 0 ? bit 4 sckp : synchronous clock polarity select bit asynchronous mode : 1 = transmit inverted data to the tx/ck pin 0 = transmit non-inverted data to the tx/ck pin synchronous mode : 1 = data is clocked on rising edge of the clock 0 = data is clocked on falling edge of the clock bit 3 brg16: 16-bit baud rate generator bit 1 = 16-bit baud rate generator is used 0 = 8-bit baud rate generator is used bit 2 unimplemented: read as ? 0 ? bit 1 wue: wake-up enable bit asynchronous mode : 1 = receiver is waiting for a falling edge. no character will be received, byte rcif will be set. wue will automatically clear after rcif is set. 0 = receiver is operating normally synchronous mode : don?t care bit 0 abden : auto-baud detect enable bit asynchronous mode : 1 = auto-baud detect mode is enabled (clears when auto-baud is complete) 0 = auto-baud detect mode is disabled synchronous mode : don?t care
pic12(l)f1840 ds41441c-page 270 ? 2011-2012 microchip technology inc. 26.4 eusart baud rate generator (brg) the baud rate generator (brg) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous eusart operation. by default, the brg operates in 8-bit mode. setting the brg16 bit of the baudcon register selects 16-bit mode. the spbrgh, spbrgl register pair determines the period of the free running baud rate timer. in asynchronous mode the multiplier of the baud rate period is determined by both the brgh bit of the txsta register and the brg16 bit of the baudcon register. in synchronous mode, the brgh bit is ignored. table 26-3 contains the formulas for determining the baud rate. example 26-1 provides a sample calculation for determining the baud rate and baud rate error. typical baud rates and error values for various asynchronous modes have been computed for your convenience and are shown in table 26-3 . it may be advantageous to use the high baud rate (brgh = 1 ), or the 16-bit brg (brg16 = 1 ) to reduce the baud rate error. the 16-bit brg mode is used to achieve slow baud rates for fast oscillator frequencies. writing a new value to the spbrgh, spbrgl register pair causes the brg timer to be reset (or cleared). this ensures that the brg does not wait for a timer overflow before outputting the new baud rate. if the system clock is changed during an active receive operation, a receive error or data loss may result. to avoid this problem, check the status of the rcidl bit to make sure that the receive operation is idle before changing the system clock. example 26-1: calculating baud rate error for a device with f osc of 16 mhz, desired baud rate of 9600, asynchronous mode, 8-bit brg: solving for spbrgh:spbrgl: x f osc desired baud rate --------------------------------------------- 64 --------------------------------------------- 1 ? = desired baud rate f osc 64 [spbrgh:spbrgl] 1 + ?? ----------------------------------------------------------------------- - = 16000000 9600 ----------------------- - 64 ----------------------- -1 ? = 25.042 ?? 25 == calculated baud rate 16000000 64 25 1 + ?? -------------------------- - = 9615 = error calc. baud rate desired baud rate ? desired baud rate -------------------------------------------------------------------------------------------- = 9615 9600 ? ?? 9600 ---------------------------------- 0 . 1 6 % ==
? 2011-2012 microchip technology inc. ds41441c-page 271 pic12(l)f1840 table 26-3: baud rate formulas table 26-4: summary of registers asso ciated with the baud rate generator configuration bits brg/eusart mode baud rate formula sync brg16 brgh 000 8-bit/asynchronous f osc /[64 (n+1)] 001 8-bit/asynchronous f osc /[16 (n+1)] 010 16-bit/asynchronous 011 16-bit/asynchronous f osc /[4 (n+1)] 10x 8-bit/synchronous 11x 16-bit/synchronous legend: x = don?t care, n = value of spbrgh, spbrgl register pair. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baudcon abdovf rcidl ? sckp brg16 ? wue abden 269 rcsta spen rx9 sren cren adden ferr oerr rx9d 268 spbrgl brg<7:0> 270 * spbrgh brg<15:8> 270 * txsta csrc tx9 txen sync sendb brgh trmt tx9d 267 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for the baud rate generator. * page provides register information.
pic12(l)f1840 ds41441c-page 272 ? 2011-2012 microchip technology inc. table 26-5: baud rates for asynchronous modes baud rate sync = 0 , brgh = 0 , brg16 = 0 f osc = 32.000 mhz f osc = 20.000 mhz f osc = 18.432 mhz f osc = 11.0592 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300?? ? ?? ? ?? ? ?? ? 1200 ? ? ? 1221 1.73 255 1200 0.00 239 1200 0.00 143 2400 2404 0.16 207 2404 0.16 129 2400 0.00 119 2400 0.00 71 9600 9615 0.16 51 9470 -1.36 32 9600 0.00 29 9600 0.00 17 10417 10417 0.00 47 10417 0.00 29 10286 -1.26 27 10165 -2.42 16 19.2k 19.23k 0.16 25 19.53k 1.73 15 19.20k 0.00 14 19.20k 0.00 8 57.6k 55.55k -3.55 3 ? ? ? 57.60k 0.00 7 57.60k 0.00 2 115.2k ? ? ? ? ? ? ? ? ? ? ? ? baud rate sync = 0 , brgh = 0 , brg16 = 0 f osc = 8.000 mhz f osc = 4.000 mhz f osc = 3.6864 mhz f osc = 1.000 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 ? ? ? 300 0.16 207 300 0.00 191 300 0.16 51 1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12 2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 ? ? ? 9600 9615 0.16 12 ? ? ? 9600 0.00 5 ? ? ? 10417 10417 0.00 11 10417 0.00 5 ? ? ? ? ? ? 19.2k ? ? ? ? ? ? 19.20k 0.00 2 ? ? ? 57.6k ? ? ? ? ? ? 57.60k 0.00 0 ? ? ? 115.2k ? ? ? ? ? ? ? ? ? ? ? ? baud rate sync = 0 , brgh = 1 , brg16 = 0 f osc = 32.000 mhz f osc = 20.000 mhz f osc = 18.432 mhz f osc = 11.0592 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 ?? ? ?? ? ?? ? ?? ? 1200 ? ? ? ? ? ? ? ? ? ? ? ? 2400 ? ? ? ? ? ? ? ? ? ?? ? 9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71 10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65 19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 57.6k 57.14k -0.79 34 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11 115.2k 117.64k 2.12 16 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5
? 2011-2012 microchip technology inc. ds41441c-page 273 pic12(l)f1840 baud rate sync = 0 , brgh = 1 , brg16 = 0 f osc = 8.000 mhz f osc = 4.000 mhz f osc = 3.6864 mhz f osc = 1.000 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 ?? ? ? ? ? ? ? ? 300 0.16 207 1200 ? ? ? 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 ? ? ? 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 ? ? ? 57.6k 55556 -3.55 8 ? ? ? 57.60k 0.00 3 ? ? ? 115.2k ? ? ? ? ? ? 115.2k 0.00 1 ? ? ? baud rate sync = 0 , brgh = 0 , brg16 = 1 f osc = 32.000 mhz f osc = 20.000 mhz f osc = 18.432 mhz f osc = 11.0592 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 300.0 0.00 6666 300.0 -0.01 4166 300.0 0.00 3839 300.0 0.00 2303 1200 1200 -0.02 3332 1200 -0.03 1041 1200 0.00 959 1200 0.00 575 2400 2401 -0.04 832 2399 -0.03 520 2400 0.00 479 2400 0.00 287 9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71 10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65 19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 57.6k 57.14k -0.79 34 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11 115.2k 117.6k 2.12 16 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5 baud rate sync = 0 , brgh = 0 , brg16 = 1 f osc = 8.000 mhz f osc = 4.000 mhz f osc = 3.6864 mhz f osc = 1.000 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207 1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 ? ? ? 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 ? ? ? 57.6k 55556 -3.55 8 ? ? ? 57.60k 0.00 3 ? ? ? 115.2k ? ? ? ? ? ? 115.2k 0.00 1 ? ? ? table 26-5: baud rates for asynchronous modes (continued)
pic12(l)f1840 ds41441c-page 274 ? 2011-2012 microchip technology inc. baud rate sync = 0 , brgh = 1 , brg16 = 1 or sync = 1 , brg16 = 1 f osc = 32.000 mhz f osc = 20.000 mhz f osc = 18.432 mhz f osc = 11.0592 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 300.0 0.00 26666 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 9215 1200 1200 0.00 6666 1200 -0.01 4166 1200 0.00 3839 1200 0.00 2303 2400 2400 0.01 3332 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151 9600 9604 0.04 832 9597 -0.03 520 9600 0.00 479 9600 0.00 287 10417 10417 0.00 767 10417 0.00 479 10425 0.08 441 10433 0.16 264 19.2k 19.18k -0.08 416 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143 57.6k 57.55k -0.08 138 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47 115.2k 115.9k 0.64 68 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23 baud rate sync = 0 , brgh = 1 , brg16 = 1 or sync = 1 , brg16 = 1 f osc = 8.000 mhz f osc = 4.000 mhz f osc = 3.6864 mhz f osc = 1.000 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832 1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207 2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103 9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25 10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23 19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12 57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 ? ? ? 115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 ? ? ? table 26-5: baud rates for asynchronous modes (continued)
? 2011-2012 microchip technology inc. ds41441c-page 275 pic12(l)f1840 26.4.1 a uto-baud detect the eusart module supports automatic detection and calibration of the baud rate. in the auto-baud detect (abd) mode, the clock to the brg is reversed. rather than the brg clocking the incoming rx signal, the rx signal is timing the brg. the baud rate generator is used to time the period of a received 55h (ascii ?u?) which is the sync character for the lin bus. the unique feature of this character is that it has five rising edges including the stop bit edge. setting the abden bit of the baudcon register starts the auto-baud calibration sequence ( figure 26-6 ). while the abd sequence takes place, the eusart state machine is held in idle. on the first rising edge of the receive line, after the start bit, the spbrg begins counting up using the brg counter clock as shown in table 26-6 . the fifth rising edge will occur on the rx pin at the end of the eighth bit period. at that time, an accumulated value totaling the proper brg period is left in the spbrgh, spbrgl register pair, the abden bit is automatically cleared and the rcif interrupt flag is set. the value in the rcreg needs to be read to clear the rcif interrupt. rcreg content should be discarded. when calibrating for modes that do not use the spbrgh register the user can verify that the spbrgl register did not overflow by checking for 00h in the spbrgh register. the brg auto-baud clock is determined by the brg16 and brgh bits as shown in tab le 2 6- 6 . during abd, both the spbrgh and spbrgl registers are used as a 16-bit counter, independent of the brg16 bit setting. while calibrating the baud rate period, the spbrgh and spbrgl registers are clocked at 1/8th the brg base clock rate. the resulting byte measurement is the average bit time when clocked at full speed. table 26-6: brg counter clock rates figure 26-6: automatic baud rate calibration note 1: if the wue bit is set with the abden bit, auto-baud detection will occur on the byte following the break character (see section 26.4 ?eusart baud rate generator (brg)? ). 2: it is up to the user to determine that the incoming character baud rate is within the range of the selected brg clock source. some combinations of oscillator frequency and eusart baud rates are not possible. 3: during the auto-baud process, the auto-baud counter starts counting at 1. upon completion of the auto-baud sequence, to achieve maximum accuracy, subtract 1 from the spbrgh:spbrgl register pair. brg16 brgh brg base clock brg abd clock 00 f osc /64 f osc /512 01 f osc /16 f osc /128 10 f osc /16 f osc /128 11 f osc /4 f osc /32 note: during the abd sequence, spbrgl and spbrgh registers are both used as a 16-bit counter, independent of brg16 setting. brg value rx pin abden bit rcif bit bit 0 bit 1 (interrupt) read rcreg brg clock start auto cleared set by user xxxxh 0000h edge #1 bit 2 bit 3 edge #2 bit 4 bit 5 edge #3 bit 6 bit 7 edge #4 stop bit edge #5 001ch note 1: the abd sequence requires the eusart module to be configured in asynchronous mode. spbrgl xxh 1ch spbrgh xxh 00h rcidl
pic12(l)f1840 ds41441c-page 276 ? 2011-2012 microchip technology inc. 26.4.2 auto-baud overflow during the course of automatic baud detection, the abdovf bit of the baudcon register will be set if the baud rate counter overflows before the fifth rising edge is detected on the rx pin. the abdovf bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the spbrgh:spbrgl register pair. after the abdovf bit has been set, the counter continues to count until the fifth rising edge is detected on the rx pin. upon detecting the fifth rx edge, the hardware will set the rcif interrupt flag and clear the abden bit of the baudcon register. the rcif flag can be subsequently cleared by reading the rcreg register. the abdovf flag of the baudcon register can be cleared by software directly. to terminate the auto-baud process before the rcif flag is set, clear the abden bit then clear the abdovf bit of the baudcon register. the abdovf bit will remain set if the abden bit is not cleared first. 26.4.3 auto-wake-up on break during sleep mode, all clocks to the eusart are suspended. because of this, the baud rate generator is inactive and a proper character reception cannot be performed. the auto-wake-up feature allows the controller to wake-up due to activity on the rx/dt line. this feature is available only in asynchronous mode. the auto-wake-up feature is enabled by setting the wue bit of the baudcon register. once set, the normal receive sequence on rx/dt is disabled, and the eusart remains in an idle state, monitoring for a wake-up event independent of the cpu mode. a wake-up event consists of a high-to-low transition on the rx/dt line. (this coincides with the start of a sync break or a wake-up signal character for the lin protocol.) the eusart module generates an rcif interrupt coincident with the wake-up event. the interrupt is generated synchronously to the q clocks in normal cpu operating modes ( figure 26-7 ), and asynchronously if the device is in sleep mode ( figure 26-8 ). the interrupt condition is cleared by reading the rcreg register. the wue bit is automatically cleared by the low-to-high transition on the rx line at the end of the break. this signals to the user that the break event is over. at this point, the eusart module is in idle mode waiting to receive the next character. 26.4.3.1 special considerations break character to avoid character errors or character fragments during a wake-up event, the wake-up character must be all zeros. when the wake-up is enabled the function works independent of the low time on the data stream. if the wue bit is set and a valid non-zero character is received, the low time from the start bit to the first rising edge will be interpreted as the wake-up event. the remaining bits in the character will be received as a fragmented character and subsequent characters can result in framing or overrun errors. therefore, the initial character in the transmission must be all ? 0 ?s. this must be 10 or more bit times, 13-bit times recommended for lin bus, or any number of bit times for standard rs-232 devices. oscillator start-up time oscillator start-up time must be considered, especially in applications using oscillators with longer start-up intervals (i.e., lp, xt or hs/pll mode). the sync break (or wake-up signal) character must be of sufficient length, and be followed by a sufficient interval, to allow enough time for the selected oscillator to start and provide proper initialization of the eusart. wue bit the wake-up event causes a receive interrupt by setting the rcif bit. the wue bit is cleared in hardware by a rising edge on rx/dt. the interrupt condition is then cleared in software by reading the rcreg register and discarding its contents. to ensure that no actual data is lost, check the rcidl bit to verify that a receive operation is not in process before setting the wue bit. if a receive operation is not occurring, the wue bit may then be set just prior to entering the sleep mode.
? 2011-2012 microchip technology inc. ds41441c-page 277 pic12(l)f1840 figure 26-7: auto-wake-up bit (wue) timing during normal operation figure 26-8: auto-wake-up bit (wue) timings during sleep q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 wue bit rx/dt line rcif bit set by user auto cleared cleared due to user read of rcreg note 1: the eusart remains in idle while the wue bit is set. q1 q2 q3 q4 q1q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 wue bit rx/dt line rcif bit set by user auto cleared cleared due to user read of rcreg sleep command executed note 1 note 1: if the wake-up event requires long oscillator warm-up time, the automatic clearing of the wue bit can occur while the stposc signal is still active. this sequence should not depend on the presence of q clocks. 2: the eusart remains in idle while the wue bit is set. sleep ends
pic12(l)f1840 ds41441c-page 278 ? 2011-2012 microchip technology inc. 26.4.4 break character sequence the eusart module has the capability of sending the special break character sequences that are required by the lin bus standard. a break character consists of a start bit, followed by 12 ? 0 ? bits and a stop bit. to send a break character, set the sendb and txen bits of the txsta register. the break character trans- mission is then initiated by a write to the txreg. the value of data written to txreg will be ignored and all ? 0 ?s will be transmitted. the sendb bit is automatically reset by hardware after the corresponding stop bit is sent. this allows the user to preload the transmit fifo with the next transmit byte following the break character (typically, the sync character in the lin specification). the trmt bit of the txsta register indicates when the transmit operation is active or idle, just as it does during normal transmission. see figure 26-9 for the timing of the break character sequence. 26.4.4.1 break and sync transmit sequence the following sequence will start a message frame header made up of a break, followed by an auto-baud sync byte. this sequence is typical of a lin bus master. 1. configure the eusart for the desired mode. 2. set the txen and sendb bits to enable the break sequence. 3. load the txreg with a dummy character to initiate transmission (the value is ignored). 4. write ?55h? to txreg to load the sync character into the transmit fifo buffer. 5. after the break has been sent, the sendb bit is reset by hardware and the sync character is then transmitted. when the txreg becomes empty, as indicated by the txif, the next data byte can be written to txreg. 26.4.5 receiving a break character the enhanced eusart module can receive a break character in two ways. the first method to detect a break character uses the ferr bit of the rcsta register and the received data as indicated by rcreg. the baud rate generator is assumed to have been initialized to the expected baud rate. a break character has been received when; ? rcif bit is set ? ferr bit is set ? rcreg = 00h the second method uses the auto-wake-up feature described in section 26.4.3 ?auto-wake-up on break? . by enabling this feature, the eusart will sample the next two transitions on rx/dt, cause an rcif interrupt, and receive the next data byte followed by another interrupt. note that following a break character, the user will typically want to enable the auto-baud detect feature. for both methods, the user can set the abden bit of the baudcon register before placing the eusart in sleep mode. figure 26-9: send break character sequence write to txreg dummy write brg output (shift clock) start bit bit 0 bit 1 bit 11 stop bit break txif bit (transmit interrupt flag) tx (pin) trmt bit (transmit shift empty flag) sendb (send break control bit) sendb sampled here auto cleared
? 2011-2012 microchip technology inc. ds41441c-page 279 pic12(l)f1840 26.5 eusart synchronous mode synchronous serial communications are typically used in systems with a single master and one or more slaves. the master device contains the necessary cir- cuitry for baud rate generation and supplies the clock for all devices in the system. slave devices can take advantage of the master clock by eliminating the inter- nal clock generation circuitry. there are two signal lines in synchronous mode: a bidi- rectional data line and a clock line. slaves use the external clock supplied by the master to shift the serial data into and out of their respective receive and trans- mit shift registers. since the data line is bidirectional, synchronous operation is half-duplex only. half-duplex refers to the fact that master and slave devices can receive and transmit data but not both simultaneously. the eusart can operate as either a master or slave device. start and stop bits are not used in synchronous trans- missions. 26.5.1 synchronous master mode the following bits are used to configure the eusart for synchronous master operation: ? sync = 1 ? csrc = 1 ? sren = 0 (for transmit); sren = 1 (for receive) ? cren = 0 (for transmit); cren = 1 (for receive) ? spen = 1 setting the sync bit of the txsta register configures the device for synchronous operation. setting the csrc bit of the txsta register configures the device as a master. clearing the sren and cren bits of the rcsta register ensures that the device is in the transmit mode, otherwise the device will be configured to receive. setting the spen bit of the rcsta register enables the eusart. 26.5.1.1 master clock synchronous data transfers use a separate clock line, which is synchronous with the data. a device config- ured as a master transmits the clock on the tx/ck line. the tx/ck pin output driver is automatically enabled when the eusart is configured for synchronous transmit or receive operation. serial data bits change on the leading edge to ensure they are valid at the trail- ing edge of each clock. one clock cycle is generated for each data bit. only as many clock cycles are gener- ated as there are data bits. 26.5.1.2 clock polarity a clock polarity option is provided for microwire compatibility. clock polarity is selected with the sckp bit of the baudcon register. setting the sckp bit sets the clock idle state as high. when the sckp bit is set, the data changes on the falling edge of each clock. clearing the sckp bit sets the idle state as low. when the sckp bit is cleared, the data changes on the rising edge of each clock. 26.5.1.3 synchronous master transmission data is transferred out of the device on the rx/dt pin. the rx/dt and tx/ck pin output drivers are automat- ically enabled when the eusart is configured for syn- chronous master transmit operation. a transmission is initiated by writing a character to the txreg register. if the tsr still contains all or part of a previous character the new character data is held in the txreg until the last bit of the previous character has been transmitted. if this is the first character, or the pre- vious character has been completely flushed from the tsr, the data in the txreg is immediately transferred to the tsr. the transmission of the character com- mences immediately following the transfer of the data to the tsr from the txreg. each data bit changes on the leading edge of the mas- ter clock and remains valid until the subsequent leading clock edge. 26.5.1.4 synchronous master transmission set-up: 1. initialize the spbrgh, spbrgl register pair and the brgh and brg16 bits to achieve the desired baud rate (see section 26.4 ?eusart baud rate generator (brg)? ). 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. disable receive mode by clearing bits sren and cren. 4. enable transmit mode by setting the txen bit. 5. if 9-bit transmission is desired, set the tx9 bit. 6. if interrupts are desired, set the txie bit of the pie1 register and the gie and peie bits of the intcon register. 7. if 9-bit transmission is selected, the ninth bit should be loaded in the tx9d bit. 8. start transmission by loading data to the txreg register. note: the tsr register is not mapped in data memory, so it is not available to the user.
pic12(l)f1840 ds41441c-page 280 ? 2011-2012 microchip technology inc. figure 26-10: synchronous transmission figure 26-11: synchronous transmis sion (through txen) table 26-7: summary of registers as sociated with synchronous master transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baudcon abdovf rcidl ? sckp brg16 ? wue abden 269 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 74 pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 75 pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 77 rcsta spen rx9 sren cren adden ferr oerr rx9d 268 spbrgl brg<7:0> 270 * spbrgh brg<15:8> 270 * txreg eusart transmit data register 259 * txsta csrc tx9 txen sync sendb brgh trmt tx9d 267 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used for synchronous master transmission. * page provides register information. bit 0 bit 1 bit 7 word 1 bit 2 bit 0 bit 1 bit 7 rx/dt write to txreg reg txif bit (interrupt flag) txen bit ? 1 ? ? 1 ? word 2 trmt bit write word 1 write word 2 note: sync master mode, spbrgl = 0 , continuous transmission of two 8-bit words. pin tx/ck pin tx/ck pin (sckp = 0 ) (sckp = 1 ) rx/dt pin tx/ck pin write to txreg reg txif bit trmt bit bit 0 bit 1 bit 2 bit 6 bit 7 txen bit
? 2011-2012 microchip technology inc. ds41441c-page 281 pic12(l)f1840 26.5.1.5 synchronous master reception data is received at the rx/dt pin. the rx/dt pin output driver is automatically disabled when the eusart is configured for synchronous master receive operation. in synchronous mode, reception is enabled by setting either the single receive enable bit (sren of the rcsta register) or the continuous receive enable bit (cren of the rcsta register). when sren is set and cren is clear, only as many clock cycles are generated as there are data bits in a single character. the sren bit is automatically cleared at the completion of one character. when cren is set, clocks are continuously generated until cren is cleared. if cren is cleared in the middle of a character the ck clock stops immediately and the partial charac- ter is discarded. if sren and cren are both set, then sren is cleared at the completion of the first character and cren takes precedence. to initiate reception, set either sren or cren. data is sampled at the rx/dt pin on the trailing edge of the tx/ck clock pin and is shifted into the receive shift register (rsr). when a complete character is received into the rsr, the rcif bit is set and the char- acter is automatically transferred to the two character receive fifo. the least significant eight bits of the top character in the receive fifo are available in rcreg. the rcif bit remains set as long as there are unread characters in the receive fifo. 26.5.1.6 slave clock synchronous data transfers use a separate clock line, which is synchronous with the data. a device configured as a slave receives the clock on the tx/ck line. the tx/ck pin output driver is automatically disabled when the device is configured for synchronous slave transmit or receive operation. serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. one data bit is transferred for each clock cycle. only as many clock cycles should be received as there are data bits. 26.5.1.7 receive overrun error the receive fifo buffer can hold two characters. an overrun error will be generated if a third character, in its entirety, is received before rcreg is read to access the fifo. when this happens the oerr bit of the rcsta register is set. previous data in the fifo will not be overwritten. the two characters in the fifo buffer can be read, however, no additional characters will be received until the error is cleared. the oerr bit can only be cleared by clearing the overrun condition. if the overrun error occurred when the sren bit is set and cren is clear then the error is cleared by reading rcreg. if the overrun occurred when the cren bit is set then the error condition is cleared by either clearing the cren bit of the rcsta register or by clearing the spen bit which resets the eusart. 26.5.1.8 receiving 9-bit characters the eusart supports 9-bit character reception. when the rx9 bit of the rcsta register is set the eusart will shift 9-bits into the rsr for each character received. the rx9d bit of the rcsta register is the ninth, and most significant, data bit of the top unread character in the receive fifo. when reading 9-bit data from the receive fifo buffer, the rx9d data bit must be read before reading the 8 least significant bits from the rcreg. 26.5.1.9 synchronous master reception set-up: 1. initialize the spbrgh, spbrgl register pair for the appropriate baud rate. set or clear the brgh and brg16 bits, as required, to achieve the desired baud rate. 2. clear the ansel bit for the rx pin (if applicable). 3. enable the synchronous master serial port by setting bits sync, spen and csrc. 4. ensure bits cren and sren are clear. 5. if interrupts are desired, set the rcie bit of the pie1 register and the gie and peie bits of the intcon register. 6. if 9-bit reception is desired, set bit rx9. 7. start reception by setting the sren bit or for continuous reception, set the cren bit. 8. interrupt flag bit rcif will be set when reception of a character is complete. an interrupt will be generated if the enable bit rcie was set. 9. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 10. read the 8-bit received data by reading the rcreg register. 11. if an overrun error occurs, clear the error by either clearing the cren bit of the rcsta register or by clearing the spen bit which resets the eusart. note: if the rx/dt function is on an analog pin, the corresponding ansel bit must be cleared for the receiver to function. note: if the device is configured as a slave and the tx/ck function is on an analog pin, the corresponding ansel bit must be cleared.
pic12(l)f1840 ds41441c-page 282 ? 2011-2012 microchip technology inc. figure 26-12: synchronous reception (master mode, sren) table 26-8: summary of registers as sociated with synchronous master reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baudcon abdovf rcidl ? sckp brg16 ? wue abden 269 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 74 pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 75 pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 77 rcreg eusart receive data register 262 * rcsta spen rx9 sren cren adden ferr oerr rx9d 268 spbrgl brg<7:0> 270 * spbrgh brg<15:8> 270 * txsta csrc tx9 txen sync sendb brgh trmt tx9d 267 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used for synchronous master reception. * page provides register information. cren bit rx/dt write to bit sren sren bit rcif bit (interrupt) read rcreg ? 0 ? bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 ? 0 ? note: timing diagram demonstrates sync master mode with bit sren = 1 and bit brgh = 0 . tx/ck pin tx/ck pin pin (sckp = 0 ) (sckp = 1 )
? 2011-2012 microchip technology inc. ds41441c-page 283 pic12(l)f1840 26.5.2 synchronous slave mode the following bits are used to configure the eusart for synchronous slave operation: ? sync = 1 ? csrc = 0 ? sren = 0 (for transmit); sren = 1 (for receive) ? cren = 0 (for transmit); cren = 1 (for receive) ? spen = 1 setting the sync bit of the txsta register configures the device for synchronous operation. clearing the csrc bit of the txsta register configures the device as a slave. clearing the sren and cren bits of the rcsta register ensures that the device is in the transmit mode, otherwise the device will be configured to receive. setting the spen bit of the rcsta register enables the eusart. 26.5.2.1 eusart synchronous slave transmit the operation of the synchronous master and slave modes are identical (see section 26.5.1.3 ?synchronous master transmission? ) , except in the case of the sleep mode. if two words are written to the txreg and then the sleep instruction is executed, the following will occur: 1. the first character will immediately transfer to the tsr register and transmit. 2. the second word will remain in txreg register. 3. the txif bit will not be set. 4. after the first character has been shifted out of tsr, the txreg register will transfer the second character to the tsr and the txif bit will now be set. 5. if the peie and txie bits are set, the interrupt will wake the device from sleep and execute the next instruction. if the gie bit is also set, the program will call the interrupt service routine. 26.5.2.2 synchronous slave transmission set-up: 1. set the sync and spen bits and clear the csrc bit. 2. clear the ansel bit for the ck pin (if applicable). 3. clear the cren and sren bits. 4. if interrupts are desired, set the txie bit of the pie1 register and the gie and peie bits of the intcon register. 5. if 9-bit transmission is desired, set the tx9 bit. 6. enable transmission by setting the txen bit. 7. if 9-bit transmission is selected, insert the most significant bit into the tx9d bit. 8. start transmission by writing the least significant 8 bits to the txreg register. table 26-9: summary of registers associated with synchronous slave transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baudcon abdovf rcidl ?sckp brg16 ? wue abden 269 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 74 pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 75 pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 77 rcsta spen rx9 sren cren adden ferr oerr rx9d 268 txreg eusart transmit data register 259 * txsta csrc tx9 txen sync sendb brgh trmt tx9d 267 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used for synchronous slave transmission. * page provides register information.
pic12(l)f1840 ds41441c-page 284 ? 2011-2012 microchip technology inc. 26.5.2.3 eusart synchronous slave reception the operation of the synchronous master and slave modes is identical ( section 26.5.1.5 ?synchronous master reception? ), with the following exceptions: ? sleep ? cren bit is always set, therefore the receiver is never idle ? sren bit, which is a ?don?t care? in slave mode a character may be received while in sleep mode by setting the cren bit prior to entering sleep. once the word is received, the rsr register will transfer the data to the rcreg register. if the rcie enable bit is set, the interrupt generated will wake the device from sleep and execute the next instruction. if the gie bit is also set, the program will branch to the interrupt vector. 26.5.2.4 synchronous slave reception set-up: 1. set the sync and spen bits and clear the csrc bit. 2. clear the ansel bit for both the ck and dt pins (if applicable). 3. if interrupts are desired, set the rcie bit of the pie1 register and the gie and peie bits of the intcon register. 4. if 9-bit reception is desired, set the rx9 bit. 5. set the cren bit to enable reception. 6. the rcif bit will be set when reception is complete. an interrupt will be generated if the rcie bit was set. 7. if 9-bit mode is enabled, retrieve the most significant bit from the rx9d bit of the rcsta register. 8. retrieve the 8 least significant bits from the receive fifo by reading the rcreg register. 9. if an overrun error occurs, clear the error by either clearing the cren bit of the rcsta register or by clearing the spen bit which resets the eusart. table 26-10: summary of registers associated with synchronous slave reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baudcon abdovf rcidl ?sckp brg16 ? wue abden 269 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 74 pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 75 pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 77 rcreg eusart receive data register 262 * rcsta spen rx9 sren cren adden ferr oerr rx9d 268 txsta csrc tx9 txen sync sendb brgh trmt tx9d 267 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used for synchronous slave reception. * page provides register information.
? 2011-2012 microchip technology inc. ds41441c-page 285 pic12(l)f1840 26.6 eusart operation during sleep the eusart will remain active during sleep only in the synchronous slave mode. all other modes require the system clock and therefore cannot generate the neces- sary signals to run the transmit or receive shift regis- ters during sleep. synchronous slave mode uses an externally generated clock to run the transmit and receive shift registers. 26.6.1 synchronous receive during sleep to receive during sleep, all the following conditions must be met before entering sleep mode: ? rcsta and txsta control registers must be configured for synchronous slave reception (see section 26.5.2.4 ?synchronous slave reception set-up:? ). ? if interrupts are desired, set the rcie bit of the pie1 register and the gie and peie bits of the intcon register. ? the rcif interrupt flag must be cleared by read- ing rcreg to unload any pending characters in the receive buffer. upon entering sleep mode, the device will be ready to accept data and clocks on the rx/dt and tx/ck pins, respectively. when the data word has been completely clocked in by the external device, the rcif interrupt flag bit of the pir1 register will be set. thereby, waking the processor from sleep. upon waking from sleep, the instruction following the sleep instruction will be executed. if the global inter- rupt enable (gie) bit of the intcon register is also set, then the interrupt service routine at address 004h will be called. 26.6.2 synchronous transmit during sleep to transmit during sleep, all the following conditions must be met before entering sleep mode: ? rcsta and txsta control registers must be configured for synchronous slave transmission (see section 26.5.2.2 ?synchronous slave transmission set-up:? ). ? the txif interrupt flag must be cleared by writing the output data to the txreg, thereby filling the tsr and transmit buffer. ? if interrupts are desired, set the txie bit of the pie1 register and the peie bit of the intcon reg- ister. ? interrupt enable bits txie of the pie1 register and peie of the intcon register must set. upon entering sleep mode, the device will be ready to accept clocks on tx/ck pin and transmit data on the rx/dt pin. when the data word in the tsr has been completely clocked out by the external device, the pending byte in the txreg will transfer to the tsr and the txif flag will be set. thereby, waking the processor from sleep. at this point, the txreg is available to accept another character for transmission, which will clear the txif flag. upon waking from sleep, the instruction following the sleep instruction will be executed. if the global interrupt enable (gie) bit is also set then the interrupt service routine at address 0004h will be called. 26.6.3 alternate pin locations this module incorporates i/o pins that can be moved to other locations with the use of the alternate pin function register, apfcon. to determine which pins can be moved and what their default locations are upon a reset, see section 12.1 ?alternate pin function? for more information.
pic12(l)f1840 ds41441c-page 286 ? 2011-2012 microchip technology inc. notes:
? 2011-2012 microchip technology inc. ds41441c-page 287 pic12(l)f1840 27.0 capacitive sensing (cps) module the capacitive sensing (cps) module allows for an interaction with an end user without a mechanical interface. in a typical application, the cps module is attached to a pad on a printed circuit board (pcb), which is electrically isolated from the end user. when the end user places their finger over the pcb pad, a capacitive load is added, causing a frequency shift in the cps module. the cps module requires software and at least one timer resource to determine the change in frequency. key features of this module include: ? analog mux for monitoring multiple inputs ? capacitive sensing oscillator ? multiple power modes ? high power range with variable voltage references ? multiple timer resources ? software control ? operation during sleep figure 27-1: capacitive sensing block diagram note 1: if cpson = 0 , disabling capacitive sensing, no channel is selected. tmr0cs cps0 cps1 cps2 cps3 cpsch<3:0> capacitive sensing oscillator cpsosc cpson cpsrng<1:0> tmr0 0 1 set tmr0if overflow t0xcs 0 1 t0cki cpsout cpsclk f osc /4 timer0 module cpson (1) t1cs<1:0> t1osc/ t1cki tmr1h:tmr1l en t1gsel<1:0> timer1 gate control logic t1g f osc f osc /4 timer1 module sync_c1out 0 1 int. ref. fvr dac ref+ ref- cpsrm 0 1
pic12(l)f1840 ds41441c-page 288 ? 2011-2012 microchip technology inc. figure 27-2: capacitive sensing oscillator block diagram note 1: module enable and power mode selections are not shown. 2: comparator remains active in noise detection mode. 0 1 v dd cpsclk oscillator module cpsx sq r + - + - (2) (1) (1) (2) 0 1 internal references fvr dac cpsrm analog pin ref- ref+
? 2011-2012 microchip technology inc. ds41441c-page 289 pic12(l)f1840 27.1 analog mux the cps module can monitor up to four inputs. see register 27-2 for details. the capacitive sensing inputs are defined as cps<7:0>, as applicable to the device. to determine if a frequency change has occurred the user must: ? select the appropriate cps pin by setting the appropriate cpsch bits of the cpscon1 register. ? set the corresponding ansel bit. ? set the corresponding tris bit. ? run the software algorithm. selection of the cpsx pin while the module is enabled will cause the capacitive sensing oscillator to be on the cpsx pin. failure to set the corresponding ansel and tris bits can cause the capacitive sensing oscillator to stop, leading to false frequency readings. 27.2 capacitive sensing oscillator the capacitive sensing oscillator consists of a constant current source and a constant current sink, to produce a triangle waveform. the cpsout bit of the cpscon0 register shows the status of the capacitive sensing oscillator, whether it is a sinking or sourcing current. the oscillator is designed to drive a capacitive load (single pcb pad) and at the same time, be a clock source to either timer0 or timer1. the oscillator has several different current settings as defined by cpsrng<1:0> of the cpscon0 register. the different current settings for the oscillator serve two purposes: ? maximize the number of counts in a timer for a fixed time base. ? maximize the count differential in the timer during a change in frequency. 27.3 voltage references the capacitive sensing oscillator uses voltage refer- ences to provide two voltage thresholds for oscillation. the upper voltage threshold is referred to as ref+ and the lower voltage threshold is referred to as ref-. the user can elect to use fixed voltage references, which are internal to the capacitive sensing oscillator, or variable voltage references, which are supplied by the fixed voltage reference (fvr) module and the digital-to-analog converter (dac) module. when the fixed voltage references are used, the v ss voltage determines the lower threshold level (ref-) and the v dd voltage determines the upper threshold level (ref+). when the variable voltage references are used, the dac voltage determines the lower threshold level (ref-) and the fvr voltage determines the upper threshold level (ref+). an advantage of using these ref- erence sources is that oscillation frequency remains constant with changes in v dd . different oscillation frequencies can be obtained through the use of these variable voltage references. the more the upper voltage reference level is lowered and the more the lower voltage reference level is raised, the higher the capacitive sensing oscillator frequency becomes. selection between the voltage references is controlled by the cpsrm bit of the cpscon0 register. setting this bit selects the variable voltage references and clearing this bit selects the fixed voltage references. please see section 14.0 ?fixed voltage reference (fvr)? and section 17.0 ?digital-to-analog converter (dac) module? for more information on configuring the variable voltage levels.
pic12(l)f1840 ds41441c-page 290 ? 2011-2012 microchip technology inc. 27.4 current ranges the capacitive sensing oscillator can operate in one of seven different power modes. the power modes are separated into two ranges; the low range and the high range. when the oscillator?s low range is selected, the fixed internal voltage references of the capacitive sensing oscillator are being used. when the oscillator?s high range is selected, the variable voltage references supplied by the fvr and dac modules are being used. selection between the voltage references is controlled by the cpsrm bit of the cpscon0 register. see section 27.3 ?voltage references? for more information. within each range there are three distinct power modes; low, medium and high. current consumption is dependent upon the range and mode selected. selecting power modes within each range is accomplished by configuring the cpsrng <1:0> bits in the cpscon0 register. see table 27-1 for proper power mode selection. the remaining mode is a noise detection mode that resides within the high range. the noise detection mode is unique in that it disables the sinking and sourc- ing of current on the analog pin but leaves the rest of the oscillator circuitry active. this reduces the oscilla- tion frequency on the analog pin to zero and also greatly reduces the current consumed by the oscillator module. when noise is introduced onto the pin, the oscillator is driven at the frequency determined by the noise. this produces a detectable signal at the comparator output, indicating the presence of activity on the pin. figure 27-2 shows a more detailed drawing of the current sources and comparators associated with the oscillator. table 27-1: current rang e mode selection cpsrm range cpsrng<1:0> current range (1) 1 variable 00 noise detection 01 low 10 medium 11 high 0 fixed 00 off 01 low 10 medium 11 high note 1: see power-down currents (i pd ) in section 30.0 ?electrical specifications? for more information.
? 2011-2012 microchip technology inc. ds41441c-page 291 pic12(l)f1840 27.5 timer resources to measure the change in frequency of the capacitive sensing oscillator, a fixed time base is required. for the period of the fixed time base, the capacitive sensing oscillator is used to clock either timer0 or timer1. the frequency of the capacitive sensing oscillator is equal to the number of counts in the timer divided by the period of the fixed time base. 27.6 fixed time base to measure the frequency of the capacitive sensing oscillator, a fixed time base is required. any timer resource or software loop can be used to establish the fixed time base. it is up to the end user to determine the method in which the fixed time base is generated. 27.6.1 timer0 to select timer0 as the timer resource for the cps module: ? set the t0xcs bit of the cpscon0 register. ? clear the tmr0cs bit of the option_reg register. when timer0 is chosen as the timer resource, the capacitive sensing oscillator will be the clock source for timer0. refer to section 20.0 ?timer0 module? for additional information. 27.6.2 timer1 to select timer1 as the timer resource for the cps module, set the tmr1cs<1:0> of the t1con register to ? 11 ?. when timer1 is chosen as the timer resource, the capacitive sensing oscillator will be the clock source for timer1. because the timer1 module has a gate control, developing a time base for the frequency measurement can be simplified by using the timer0 overflow flag. it is recommend that the timer0 overflow flag, in conjunction with the toggle mode of the timer1 gate, be used to develop the fixed time base required by the software portion of the cps module. refer to section 21.6 ?timer1 gate? for additional information. table 27-2: timer1 enable function 27.7 software control the software portion of the cps module is required to determine the change in frequency of the capacitive sensing oscillator. this is accomplished by the following: ? setting a fixed time base to acquire counts on timer0 or timer1. ? establishing the nominal frequency for the capacitive sensing oscillator. ? establishing the reduced frequency for the capac- itive sensing oscillator due to an additional capac- itive load. ? set the frequency threshold. 27.7.1 nominal frequency (no capacitive load) to determine the nominal frequency of the capacitive sensing oscillator: ? remove any extra capacitive load on the selected cpsx pin. ? at the start of the fixed time base, clear the timer resource. ? at the end of the fixed time base save the value in the timer resource. the value of the timer resource is the number of oscillations of the capacitive sensing oscillator for the given time base. the frequency of the capacitive sensing oscillator is equal to the number of counts on in the timer, divided by the period of the fixed time base. 27.7.2 reduced frequency (additional capacitive load) the extra capacitive load will cause the frequency of the capacitive sensing oscillator to decrease. to determine the reduced frequency of the capacitive sensing oscillator: ? add a typical capacitive load on the selected cpsx pin. ? use the same fixed time base as the nominal frequency measurement. ? at the start of the fixed time base, clear the timer resource. ? at the end of the fixed time base, save the value in the timer resource. the value of the timer resource is the number of oscil- lations of the capacitive sensing oscillator with an addi- tional capacitive load. the frequency of the capacitive sensing oscillator is equal to the number of counts on in the timer, divided by the period of the fixed time base. this frequency should be less than the value obtained during the nominal frequency measurement. note: the fixed time base can not be generated by the timer resource that the capacitive sensing oscillator is clocking. tmr1on tmr1ge timer1 operation 00 off 01 off 10 on 11 count enabled by input
pic12(l)f1840 ds41441c-page 292 ? 2011-2012 microchip technology inc. 27.7.3 frequency threshold the frequency threshold should be placed midway between the value of nominal frequency and the reduced frequency of the capacitive sensing oscillator. refer to application note an1103, ? software handling for capacitive sensing ? (ds01103) for more detailed information on the software required for cps module. 27.8 operation during sleep the capacitive sensing oscillator will continue to run as long as the module is enabled, independent of the part being in sleep. in order for the software to determine if a frequency change has occurred, the part must be awake. however, the part does not have to be awake when the timer resource is acquiring counts. note: for more information on general capacitive sensing refer to application notes: ? an1101, ? introduction to capacitive sensing ? (ds01101) ? an1102, ? layout and physical design guidelines for capacitive sensing ? (ds01102) note: timer0 does not operate when in sleep, and therefore, cannot be used for capacitive sense measurements in sleep.
? 2011-2012 microchip technology inc. ds41441c-page 293 pic12(l)f1840 27.9 register definitions: capacitive sensing control register 27-1: cpscon0: capaciti ve sensing control register 0 r/w-0/0 r/w-0/0 u-0 u-0 r/w-0/0 r/w-0/0 r-0/0 r/w-0/0 cpson cpsrm ? ? cpsrng<1:0> cpsout t0xcs bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 cpson: cps module enable bit 1 = cps module is enabled 0 = cps module is disabled bit 6 cpsrm: capacitive sensing reference mode bit 1 = capacitive sensing module is in variable voltage reference mode. 0 = capacitive sensing module is in fixed voltage reference mode. bit 5-4 unimplemented: read as ? 0 ? bit 3-2 cpsrng<1:0>: capacitive sensing current range bit if cpsrm = 1 (variable voltage reference mode): (2) 11 = oscillator is in high current range. 10 = oscillator is in medium current range. 01 = oscillator is in low current range. 00 = oscillator is on. noise detection mode. if cpsrm = 0 (fixed voltage reference mode): (1) 11 = oscillator is in high current range. 10 = oscillator is in medium current range. 01 = oscillator is in low current range. 00 = oscillator is off. bit 1 cpsout: capacitive sensing oscillator status bit 1 = oscillator is sourcing current (current flowing out of the pin) 0 = oscillator is sinking current (current flowing into the pin) bit 0 t0xcs: timer0 external clock source select bit if tmr0cs = 1 : the t0xcs bit controls which clock external to the core/timer0 module supplies timer0: 1 = timer0 clock source is the capacitive sensing oscillator, cpsclk 0 = timer0 clock source is the t0cki pin if tmr0cs = 0 : timer0 clock source is controlled by the core/timer0 module and is f osc /4
pic12(l)f1840 ds41441c-page 294 ? 2011-2012 microchip technology inc. table 27-3: summary of registers as sociated with capacitive sensing register 27-2: cpscon1: capaciti ve sensing control register 1 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0/0 r/w-0/0 ? ? ? ? ? ? cpsch<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-2 unimplemented: read as ? 0 ? bit 1-0 cpsch<1:0>: capacitive sensing channel select bits if cpson = 0 : these bits are ignored. no channel is selected. if cpson = 1 : 11 = channel 3, (cps3) 10 = channel 2, (cps2) 01 = channel 1, (cps1) 00 = channel 0, (cps0) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ansela ? ? ?ansa4 ? ansa2 ansa1 ansa0 106 cpscon0 cpson cpsrm ? ? cpsrng<1:0> cpsout t0xcs 293 cpscon1 ? ? ? ? ? ? cpsch<1:0> 294 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 74 option_reg wpuen intedg tmr0cs tmr0se psa ps<2:0> 151 t1con tmr1cs<1:0> t1ckps<1:0> t1oscen t1sync ?tmr1on 161 trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 105 legend: ? = unimplemented locations, read as ? 0 ?. shaded cells are not used by the cps module.
? 2011-2012 microchip technology inc. ds41441c-page 295 pic12(l)f1840 28.0 in-circuit serial programming? (icsp?) icsp? programming allows customers to manufacture circuit boards with unprogrammed devices. programming can be done after the assembly process allowing the device to be programmed with the most recent firmware or a custom firmware. five pins are needed for icsp? programming: ? icspclk ? icspdat ?mclr /v pp ?v dd ?v ss in program/verify mode the program memory, user ids and the configuration words are programmed through serial communications. the icspdat pin is a bidirec- tional i/o used for transferring the serial data and the icspclk pin is the clock input. for more information on icsp? refer to the ? pic16f/lf1847/pic12f/lf1840 memory programming specification ?, (ds41439). 28.1 high-voltage programming entry mode the device is placed into high-voltage programming entry mode by holding the icspclk and icspdat pins low then raising the voltage on mclr /v pp to v ihh . some programmers produce v pp greater than v ihh (9.0v), an external circuit is required to limit the v pp voltage. see figure 28-1 for example circuit. figure 28-1: vpp limiter example circuit v ref v pp v dd v ss icsp_data icsp_clock nc rj11-6pin rj11-6pin r1 270 ohm to m p l a b ? icd 2 to tar g e t b o ar d 1 2 3 4 5 61 2 3 4 5 6 r2 r3 10k 1% 24k 1% u1 lm431bcmx a 2 3 6 7 8 a a a k nc nc 1 4 5 note: the mplab icd 2 produces a v pp voltage greater than the maximum v pp specification of the pic12f/lf1840.
pic12(l)f1840 ds41441c-page 296 ? 2011-2012 microchip technology inc. 28.2 low-voltage programming entry mode the low-voltage programming entry mode allows the pic ? flash mcus to be programmed using v dd only, without high voltage. when the lvp bit of configuration words is set to ? 1 ?, the low-voltage icsp programming entry is enabled. to disable the low-voltage icsp mode, the lvp bit must be programmed to ? 0 ?. entry into the low-voltage programming entry mode requires the following steps: 1. mclr is brought to v il . 2. a 32-bit key sequence is presented on icspdat, while clocking icspclk. once the key sequence is complete, mclr must be held at v il for as long as program/verify mode is to be maintained. if low-voltage programming is enabled (lvp = 1 ), the mclr reset function is automatically enabled and cannot be disabled. see section 7.4 ?mclr? for more information. the lvp bit can only be reprogrammed to ? 0 ? by using the high-voltage programming mode. 28.3 common programming interfaces connection to a target device is typically done through an icsp? header. a commonly found connector on development tools is the rj-11 in the 6p6c (6 pin, 6 connector) configuration. see figure 28-2 . figure 28-2: icd rj-11 style connector interface another connector often found in use with the pickit? programmers is a standard 6-pin header with 0.1 inch spacing. refer to figure 28-3 . figure 28-3: pickit? programme r style connector interface 1 2 3 4 5 6 target bottom side pc board v pp /mclr v ss icspclk v dd icspdat nc pin description* 1 = v pp /mclr 2 = v dd target 3 = v ss (ground) 4 = icspdat 5 = icspclk 6 = no connect 1 2 3 4 5 6 * the 6-pin header (0.100" spacing) accepts 0.025" square pins. pin description* 1 = v pp /mclr 2 = v dd target 3 = v ss (ground) 4 = icspdat 5 = icspclk 6 = no connect pin 1 indicator
? 2011-2012 microchip technology inc. ds41441c-page 297 pic12(l)f1840 for additional interface recommendations, refer to your specific device programmer manual prior to pcb design. it is recommended that isolation devices be used to separate the programming pins from other circuitry. the type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. see figure 28-4 for more information. figure 28-4: typical connect ion for icsp? programming v dd v pp v ss external device to be data clock v dd mclr /v pp v ss icspdat icspclk * * * to normal connections * isolation devices (as required). programming signals programmed v dd
pic12(l)f1840 ds41441c-page 298 ? 2011-2012 microchip technology inc. notes:
? 2011-2012 microchip technology inc. ds41441c-page 299 pic12(l)f1840 29.0 instruction set summary each instruction is a 14-bit word containing the opera- tion code (opcode) and all required operands. the opcodes are broken into three broad categories. ? byte oriented ? bit oriented ? literal and control the literal and control category contains the most var- ied instruction word format. table 29-3 lists the instructions recognized by the mpasm tm assembler. all instructions are executed within a single instruction cycle, with the following exceptions, which may take two or three cycles: ? subroutine takes two cycles ( call , callw ) ? returns from interrupts or subroutines take two cycles ( return , retlw , retfie ) ? program branching takes two cycles ( goto , bra , brw , btfss , btfsc , decfsz , incsfz ) ? one additional instruction cycle will be used when any instruction references an indirect file register and the file select register is pointing to program memory. one instruction cycle consists of 4 oscillator cycles; for an oscillator frequency of 4 mhz, this gives a nominal instruction execution rate of 1 mhz. all instruction examples use the format ? 0xhh ? to represent a hexadecimal number, where ? h ? signifies a hexadecimal digit. 29.1 read-modify-write operations any instruction that specifies a file register as part of the instruction performs a read-modify-write (r-m-w) operation. the register is read, the data is modified, and the result is stored according to either the instruc- tion, or the destination designator ?d?. a read operation is performed on a register even if the instruction writes to that register. table 29-1: opcode field descriptions table 29-2: abbreviation descriptions field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don?t care location (= 0 or 1 ). the assembler will generate code with x = 0 . it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0 : store result in w , d = 1 : store result in file register f. default is d = 1. n fsr or indf number. (0-1) mm pre-post increment-decrement mode selection field description pc program counter to time-out bit c carry bit dc digit carry bit z zero bit pd power-down bit
pic12(l)f1840 ds41441c-page 300 ? 2011-2012 microchip technology inc. figure 29-1: general format for instructions byte-oriented file register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit file register address bit-oriented file register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit file register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only movlp instruction only 13 5 4 0 opcode k (literal) k = 5-bit immediate value movlb instruction only 13 9 8 0 opcode k (literal) k = 9-bit immediate value bra instruction only fsr offset instructions 13 7 6 5 0 opcode n k (literal) n = appropriate fsr fsr increment instructions 13 7 6 0 opcode k (literal) k = 7-bit immediate value 13 3 2 1 0 opcode n m (mode) n = appropriate fsr m = 2-bit mode value k = 6-bit immediate value 13 0 opcode opcode only
? 2011-2012 microchip technology inc. ds41441c-page 301 pic12(l)f1840 table 29-3: pic12f/lf1840 instruction set mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf addwfc andwf asrf lslf lsrf clrf clrw comf decf incf iorwf movf movwf rlf rrf subwf subwfb swapf xorwf f, d f, d f, d f, d f, d f, d f ? f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d add w and f add with carry w and f and w with f arithmetic right shift logical left shift logical right shift clear f clear w complement f decrement f increment f inclusive or w with f move f move w to f rotate left f through carry rotate right f through carry subtract w from f subtract with borrow w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 00 11 00 11 11 11 00 00 00 00 00 00 00 00 00 00 00 11 00 00 0111 1101 0101 0111 0101 0110 0001 0001 1001 0011 1010 0100 1000 0000 1101 1100 0010 1011 1110 0110 dfff dfff dfff dfff dfff dfff lfff 0000 dfff dfff dfff dfff dfff 1fff dfff dfff dfff dfff dfff dfff ffff ffff ffff ffff ffff ffff ffff 00xx ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff c, dc, z c, dc, z z c, z c, z c, z z z z z z z z c c c, dc, z c, dc, z z 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 byte oriented skip operations decfsz incfsz f, d f, d decrement f, skip if 0 increment f, skip if 0 1(2) 1(2) 00 00 1011 1111 dfff dfff ffff ffff 1, 2 1, 2 bit-oriented file register operations bcf bsf f, b f, b bit clear f bit set f 1 1 01 01 00bb 01bb bfff bfff ffff ffff 2 2 bit-oriented skip operations btfsc btfss f, b f, b bit test f, skip if clear bit test f, skip if set 1 (2) 1 (2) 01 01 10bb 11bb bfff bfff ffff ffff 1, 2 1, 2 literal operations addlw andlw iorlw movlb movlp movlw sublw xorlw k k k k k k k k add literal and w and literal with w inclusive or literal with w move literal to bsr move literal to pclath move literal to w subtract w from literal exclusive or literal with w 1 1 1 1 1 1 1 1 11 11 11 00 11 11 11 11 1110 1001 1000 0000 0001 0000 1100 1010 kkkk kkkk kkkk 001k 1kkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk c, dc, z z z c, dc, z z note 1: if the program counter (pc) is modified, or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 2: if this instruction addresses an indf register and the msb of the corresponding fsr is set, this instruction will require one additional instruction cycle.
pic12(l)f1840 ds41441c-page 302 ? 2011-2012 microchip technology inc. table 29-3: pic12f/lf1840 instruction set (continued) mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb control operations bra brw call callw goto retfie retlw return k ? k ? k k k ? relative branch relative branch with w call subroutine call subroutine with w go to address return from interrupt return with literal in w return from subroutine 2 2 2 2 2 2 2 2 11 00 10 00 10 00 11 00 001k 0000 0kkk 0000 1kkk 0000 0100 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 1011 kkkk 1010 kkkk 1001 kkkk 1000 inherent operations clrwdt nop option reset sleep tris ? ? ? ? ? f clear watchdog timer no operation load option_reg register with w software device reset go into standby mode load tris register with w 1 1 1 1 1 1 00 00 00 00 00 00 0000 0000 0000 0000 0000 0000 0110 0000 0110 0000 0110 0110 0100 0000 0010 0001 0011 0fff to , pd to , pd c-compiler optimized addfsr moviw movwi n, k n mm k[n] n mm k[n] add literal k to fsrn move indirect fsrn to w with pre/post inc/dec modifier, mm move indfn to w, indexed indirect. move w to indirect fsrn with pre/post inc/dec modifier, mm move w to indfn, indexed indirect. 1 1 1 1 1 11 00 11 00 11 0001 0000 1111 0000 1111 0nkk 0001 0nkk 0001 1nkk kkkk 0nmm kkkk 1nmm kkkk z z 2, 3 2 2, 3 2 note 1: if the program counter (pc) is modified, or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 2: if this instruction addresses an indf register and the msb of the corresponding fsr is set, this instruction will require one additional instruction cycle. 3: see table in the moviw and movwi instruction descriptions.
? 2011-2012 microchip technology inc. ds41441c-page 303 pic12(l)f1840 29.2 instruction descriptions addfsr add literal to fsrn syntax: [ label ] addfsr fsrn, k operands: -32 ? k ? 31 n ? [ 0, 1] operation: fsr(n) + k ? fsr(n) status affected: none description: the signed 6-bit literal ?k? is added to the contents of the fsrnh:fsrnl register pair. fsrn is limited to the range 0000h - ffffh. moving beyond these bounds will cause the fsr to wrap-around. addlw add literal and w syntax: [ label ] addlw k operands: 0 ? k ? 255 operation: (w) + k ? (w) status affected: c, dc, z description: the contents of the w register are added to the eight-bit literal ?k? and the result is placed in the w register. addwf add w and f syntax: [ label ] addwf f,d operands: 0 ? f ? 127 d ??? 0 , 1 ? operation: (w) + (f) ? (destination) status affected: c, dc, z description: add the contents of the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. addwfc add w and carry bit to f syntax: [ label ] addwfc f {,d} operands: 0 ? f ? 127 d ?? [0,1] operation: (w) + (f) + (c) ? dest status affected: c, dc, z description: add w, the carry flag and data mem- ory location ?f?. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed in data memory location ?f?. andlw and literal with w syntax: [ label ] andlw k operands: 0 ? k ? 255 operation: (w) .and. (k) ? (w) status affected: z description: the contents of w register are and?ed with the eight-bit literal ?k?. the result is placed in the w register. andwf and w with f syntax: [ label ] andwf f,d operands: 0 ? f ? 127 d ??? 0 , 1 ? operation: (w) .and. (f) ? (destination) status affected: z description: and the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. asrf arithmetic right shift syntax: [ label ] asrf f {,d} operands: 0 ? f ? 127 d ?? [0,1] operation: (f<7>) ? dest<7> (f<7:1>) ? dest<6:0>, (f<0>) ? c, status affected: c, z description: the contents of register ?f? are shifted one bit to the right through the carry flag. the msb remains unchanged. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is stored back in reg- ister ?f?. register f c
pic12(l)f1840 ds41441c-page 304 ? 2011-2012 microchip technology inc. bcf bit clear f syntax: [ label ] bcf f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: 0 ? (f) status affected: none description: bit ?b? in register ?f? is cleared. bra relative branch syntax: [ label ] bra label [ label ] bra $+k operands: -256 ? label - pc + 1 ? 255 -256 ? k ? 255 operation: (pc) + 1 + k ? pc status affected: none description: add the signed 9-bit literal ?k? to the pc. since the pc will have incre- mented to fetch the next instruction, the new address will be pc + 1 + k. this instruction is a two-cycle instruc- tion. this branch has a limited range. brw relative branch with w syntax: [ label ] brw operands: none operation: (pc) + (w) ? pc status affected: none description: add the contents of w (unsigned) to the pc. since the pc will have incre- mented to fetch the next instruction, the new address will be pc + 1 + (w). this instruction is a two-cycle instruc- tion. bsf bit set f syntax: [ label ] bsf f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: 1 ? (f) status affected: none description: bit ?b? in register ?f? is set. btfsc bit test f, skip if clear syntax: [ label ] btfsc f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: skip if (f) = 0 status affected: none description: if bit ?b? in register ?f? is ? 1 ?, the next instruction is executed. if bit ?b?, in register ?f?, is ? 0 ?, the next instruction is discarded, and a nop is executed instead, making this a 2-cycle instruction. btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 ? f ? 127 0 ? b < 7 operation: skip if (f) = 1 status affected: none description: if bit ?b? in register ?f? is ? 0 ?, the next instruction is executed. if bit ?b? is ? 1 ?, then the next instruction is discarded and a nop is executed instead, making this a 2-cycle instruction.
? 2011-2012 microchip technology inc. ds41441c-page 305 pic12(l)f1840 call call subroutine syntax: [ label ] call k operands: 0 ? k ? 2047 operation: (pc)+ 1 ? tos, k ? pc<10:0>, (pclath<6:3>) ? pc<14:11> status affected: none description: call subroutine. first, return address (pc + 1) is pushed onto the stack. the eleven-bit immediate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pclath. call is a two-cycle instruc- tion. callw subroutine call with w syntax: [ label ] callw operands: none operation: (pc) +1 ? tos, (w) ? pc<7:0>, (pclath<6:0>) ?? pc<14:8> status affected: none description: subroutine call with w. first, the return address (pc + 1) is pushed onto the return stack. then, the con- tents of w is loaded into pc<7:0>, and the contents of pclath into pc<14:8>. callw is a two-cycle instruction. clrf clear f syntax: [ label ] clrf f operands: 0 ? f ? 127 operation: 00h ? (f) 1 ? z status affected: z description: the contents of register ?f? are cleared and the z bit is set. clrw clear w syntax: [ label ] clrw operands: none operation: 00h ? (w) 1 ? z status affected: z description: w register is cleared. zero bit (z) is set. clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h ? wdt 0 ? wdt prescaler, 1 ? to 1 ? pd status affected: to , pd description: clrwdt instruction resets the watch- dog timer. it also resets the prescaler of the wdt. status bits to and pd are set. comf complement f syntax: [ label ] comf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f ) ? (destination) status affected: z description: the contents of register ?f? are com- plemented. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. decf decrement f syntax: [ label ] decf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) - 1 ? (destination) status affected: z description: decrement register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?.
pic12(l)f1840 ds41441c-page 306 ? 2011-2012 microchip technology inc. decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) - 1 ? (destination); skip if result = 0 status affected: none description: the contents of register ?f? are decre- mented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 1 ?, the next instruction is executed. if the result is ? 0 ?, then a nop is executed instead, making it a 2-cycle instruction. goto unconditional branch syntax: [ label ] goto k operands: 0 ? k ? 2047 operation: k ? pc<10:0> pclath<6:3> ? pc<14:11> status affected: none description: goto is an unconditional branch. the eleven-bit immediate value is loaded into pc bits <10:0>. the upper bits of pc are loaded from pclath<4:3>. goto is a two-cycle instruction. incf increment f syntax: [ label ] incf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) + 1 ? (destination) status affected: z description: the contents of register ?f? are incre- mented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) + 1 ? (destination), skip if result = 0 status affected: none description: the contents of register ?f? are incre- mented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 1 ?, the next instruction is executed. if the result is ? 0 ?, a nop is executed instead, making it a 2-cycle instruction. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 ? k ? 255 operation: (w) .or. k ? (w) status affected: z description: the contents of the w register are or?ed with the eight-bit literal ?k?. the result is placed in the w register. iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (w) .or. (f) ? (destination) status affected: z description: inclusive or the w register with regis- ter ?f?. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?.
? 2011-2012 microchip technology inc. ds41441c-page 307 pic12(l)f1840 lslf logical left shift syntax: [ label ] lslf f {,d} operands: 0 ? f ? 127 d ?? [0,1] operation: (f<7>) ? c (f<6:0>) ? dest<7:1> 0 ? dest<0> status affected: c, z description: the contents of register ?f? are shifted one bit to the left through the carry flag. a ? 0 ? is shifted into the lsb. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. lsrf logical right shift syntax: [ label ] lsrf f {,d} operands: 0 ? f ? 127 d ?? [0,1] operation: 0 ? dest<7> (f<7:1>) ? dest<6:0>, (f<0>) ? c, status affected: c, z description: the contents of register ?f? are shifted one bit to the right through the carry flag. a ? 0 ? is shifted into the msb. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. register f 0 c register f c 0 movf move f syntax: [ label ] movf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) ? (dest) status affected: z description: the contents of register f is moved to a destination dependent upon the status of d. if d = 0 , destination is w register. if d = 1 , the destination is file register f itself. d = 1 is useful to test a file register since status flag z is affected. words: 1 cycles: 1 example: movf fsr, 0 after instruction w = value in fsr register z= 1
pic12(l)f1840 ds41441c-page 308 ? 2011-2012 microchip technology inc. moviw move indfn to w syntax: [ label ] moviw ++fsrn [ label ] moviw --fsrn [ label ] moviw fsrn++ [ label ] moviw fsrn-- [ label ] moviw k[fsrn] operands: n ? [ 0 , 1 ] mm ? [ 00 , 01 , 10 , 11 ] -32 ? k ? 31 operation: indfn ? w effective address is determined by ? fsr + 1 (preincrement) ? fsr - 1 (predecrement) ? fsr + k (relative offset) after the move, the fsr value will be either: ? fsr + 1 (all increments) ? fsr - 1 (all decrements) ? unchanged status affected: z mode syntax mm preincrement ++fsrn 00 predecrement --fsrn 01 postincrement fsrn++ 10 postdecrement fsrn-- 11 description: this instruction is used to move data between w and one of the indirect registers (indfn). before/after this move, the pointer (fsrn) is updated by pre/post incrementing/decrementing it. note: the indfn registers are not physical registers. any instruction that accesses an indfn register actually accesses the register at the address specified by the fsrn. fsrn is limited to the range 0000h - ffffh. incrementing/decrementing it beyond these bounds will cause it to wrap around. movlb move literal to bsr syntax: [ label ] movlb k operands: 0 ? k ? 15 operation: k ? bsr status affected: none description: the five-bit literal ?k? is loaded into the bank select register (bsr). movlp move literal to pclath syntax: [ label ] movlp k operands: 0 ? k ? 127 operation: k ? pclath status affected: none description: the seven-bit literal ?k? is loaded into the pclath register. movlw move literal to w syntax: [ label ] movlw k operands: 0 ? k ? 255 operation: k ? (w) status affected: none description: the eight-bit literal ?k? is loaded into w register. the ?don?t cares? will assem- ble as ? 0 ?s. words: 1 cycles: 1 example: movlw 0x5a after instruction w = 0x5a movwf move w to f syntax: [ label ] movwf f operands: 0 ? f ? 127 operation: (w) ? (f) status affected: none description: move data from w register to register ?f?. words: 1 cycles: 1 example: movwf option_reg before instruction option_reg = 0xff w = 0x4f after instruction option_reg = 0x4f w = 0x4f
? 2011-2012 microchip technology inc. ds41441c-page 309 pic12(l)f1840 movwi move w to indfn syntax: [ label ] movwi ++fsrn [ label ] movwi --fsrn [ label ] movwi fsrn++ [ label ] movwi fsrn-- [ label ] movwi k[fsrn] operands: n ? [ 0 , 1 ] mm ? [ 00 , 01 , 10 , 11 ] -32 ? k ? 31 operation: w ? indfn effective address is determined by ? fsr + 1 (preincrement) ? fsr - 1 (predecrement) ? fsr + k (relative offset) after the move, the fsr value will be either: ? fsr + 1 (all increments) ? fsr - 1 (all decrements) unchanged status affected: none mode syntax mm preincrement ++fsrn 00 predecrement --fsrn 01 postincrement fsrn++ 10 postdecrement fsrn-- 11 description: this instruction is used to move data between w and one of the indirect registers (indfn). before/after this move, the pointer (fsrn) is updated by pre/post incrementing/decrementing it. note: the indfn registers are not physical registers. any instruction that accesses an indfn register actually accesses the register at the address specified by the fsrn. fsrn is limited to the range 0000h - ffffh. incrementing/decrementing it beyond these bounds will cause it to wrap-around. the increment/decrement operation on fsrn will not affect any status bits. nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none description: no operation. words: 1 cycles: 1 example: nop option load option_reg register with w syntax: [ label ] option operands: none operation: (w) ? option_reg status affected: none description: move data from w register to option_reg register. words: 1 cycles: 1 example: option before instruction option_reg = 0xff w = 0x4f after instruction option_reg = 0x4f w = 0x4f reset software reset syntax: [ label ] reset operands: none operation: execute a device reset. resets the r i flag of the pcon register. status affected: none description: this instruction provides a way to execute a hardware reset by soft- ware.
pic12(l)f1840 ds41441c-page 310 ? 2011-2012 microchip technology inc. retfie return from interrupt syntax: [ label ] retfie operands: none operation: tos ? pc, 1 ? gie status affected: none description: return from interrupt. stack is poped and top-of-stack (tos) is loaded in the pc. interrupts are enabled by setting global interrupt enable bit, gie (intcon<7>). this is a two-cycle instruction. words: 1 cycles: 2 example: retfie after interrupt pc = tos gie = 1 retlw return with literal in w syntax: [ label ] retlw k operands: 0 ? k ? 255 operation: k ? (w); tos ? pc status affected: none description: the w register is loaded with the eight bit literal ?k?. the program counter is loaded from the top of the stack (the return address). this is a two-cycle instruction. words: 1 cycles: 2 example: table call table;w contains table ;offset value ? ;w now has table value ? ? addwf pc ;w = offset retlw k1 ;begin table retlw k2 ; ? ? ? retlw kn ; end of table before instruction w = 0x07 after instruction w = value of k8 return return from subroutine syntax: [ label ] return operands: none operation: tos ? pc status affected: none description: return from subroutine. the stack is poped and the top of the stack (tos) is loaded into the program counter. this is a two-cycle instruction. rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: see description below status affected: c description: the contents of register ?f? are rotated one bit to the left through the carry flag. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. words: 1 cycles: 1 example: rlf reg1,0 before instruction reg1 = 1110 0110 c=0 after instruction reg1 = 1110 0110 w = 1100 1100 c=1 register f c
? 2011-2012 microchip technology inc. ds41441c-page 311 pic12(l)f1840 rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: see description below status affected: c description: the contents of register ?f? are rotated one bit to the right through the carry flag. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. sleep enter sleep mode syntax: [ label ]sleep operands: none operation: 00h ? wdt, 0 ? wdt prescaler, 1 ? to , 0 ? pd status affected: to , pd description: the power-down status bit, pd is cleared. time-out status bit, to is set. watchdog timer and its pres- caler are cleared. the processor is put into sleep mode with the oscillator stopped. register f c sublw subtract w from literal syntax: [ label ]sublw k operands: 0 ?? k ?? 255 operation: k - (w) ??? w) status affected: c, dc, z description: the w register is subtracted (2?s com- plement method) from the eight-bit literal ?k?. the result is placed in the w register. subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 ?? f ?? 127 d ? [ 0 , 1 ] operation: (f) - (w) ??? destination) status affected: c, dc, z description: subtract (2?s complement method) w register from register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f. subwfb subtract w from f with borrow syntax: subwfb f {,d} operands: 0 ? f ? 127 d ? [0,1] operation: (f) ? (w) ? (b ) ?? dest status affected: c, dc, z description: subtract w and the borrow flag (carry) from register ?f? (2?s comple- ment method). if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. c = 0 w ? k c = 1 w ? k dc = 0 w<3:0> ? k<3:0> dc = 1 w<3:0> ? k<3:0> c = 0 w ? f c = 1 w ? f dc = 0 w<3:0> ? f<3:0> dc = 1 w<3:0> ? f<3:0>
pic12(l)f1840 ds41441c-page 312 ? 2011-2012 microchip technology inc. swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f<3:0>) ? (destination<7:4>), (f<7:4>) ? (destination<3:0>) status affected: none description: the upper and lower nibbles of regis- ter ?f? are exchanged. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed in register ?f?. tris load tris register with w syntax: [ label ] tris f operands: 5 ? f ? 7 operation: (w) ? tris register ?f? status affected: none description: move data from w register to tris register. when ?f? = 5, trisa is loaded. when ?f? = 6, trisb is loaded. when ?f? = 7, trisc is loaded. xorlw exclusive or literal with w syntax: [ label ]xorlw k operands: 0 ?? k ?? 255 operation: (w) .xor. k ??? w) status affected: z description: the contents of the w register are xor?ed with the eight-bit literal ?k?. the result is placed in the w register. xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (w) .xor. (f) ??? destination) status affected: z description: exclusive or the contents of the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in regis- ter ?f?.
? 2011-2012 microchip technology inc. ds41441c-page 313 pic12(l)f1840 30.0 electrical specifications absolute maximum ratings (?) ambient temperature under bias................................................................................................. ...... -40c to +125c storage temperature ............................................................................................................ ............ -65c to +150c voltage on v dd with respect to v ss , pic12f1840 ............................................................................. -0.3v to +6.5v voltage on v dd with respect to v ss , pic12lf1840 ........................................................................... -0.3v to +4.0v voltage on mclr with respect to vss ................................................................................................. -0.3v to +9.0v voltage on all other pins with respect to v ss ........................................................................... -0.3v to (v dd + 0.3v) total power dissipation (1) ............................................................................................................................... 800 mw maximum current out of v ss pin, -40c ? t a ? +85c for industrial................................................................. 85 ma maximum current out of v ss pin, -40c ? t a ? +125c for extended .............................................................. 35 ma maximum current into v dd pin, -40c ? t a ? +85c for industrial.................................................................... 85 ma maximum current into v dd pin, -40c ? t a ? +125c for extended ................................................................. 35 ma clamp current, i k (v pin < 0 or v pin > v dd ) ??????????????????????????????????????????????????????????????? ??????????????????????????????????????????????????? 20 ma maximum output current sunk by any i/o pin..................................................................................... ............... 25 ma maximum output current sourced by any i/o pin .................................................................................. ............ 25 ma note 1: power dissipation is calculated as follows: p dis = v dd x {i dd ? ? i oh } + ? {(v dd ? v oh ) x i oh } + ? (v o l x i ol ). ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic12(l)f1840 ds41441c-page 314 ? 2011-2012 microchip technology inc. figure 30-1: pic12f1840 voltag e frequency graph, -40c ? t a ?? +125c figure 30-2: pic12lf1840 volt age frequency graph, -40c ? t a ?? +125c note 1: the shaded region indicates the permissible combinations of voltage and frequency. 2: refer to table 30-1 for each oscillator mode?s supported frequencies. 2.3 0 2.5 frequency (mhz) v dd (v) 432 10 16 5.5 1.8 note 1: the shaded region indicates the permissible combinations of voltage and frequency. 2: refer to table 30-1 for each oscillator mode?s supported frequencies. 1.8 0 2.5 frequency (mhz) v dd (v) 432 10 16 3.6
? 2011-2012 microchip technology inc. ds41441c-page 315 pic12(l)f1840 figure 30-3: hfintosc frequency accuracy over device v dd and temperature 125 25 2.0 0 60 85 v dd (v) 4.0 5.0 4.5 temperature ( c ) 2.5 3.0 3.5 5.5 1.8 -40 5% 2% 5% 3%
pic12(l)f1840 ds41441c-page 316 ? 2011-2012 microchip technology inc. 30.1 dc characteristics: supply voltage pic12lf1840 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended pic12f1840 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param. no. sym. characteristic min. typ? max. units conditions d001 v dd supply voltage (v ddmin , v ddmax ) 1.8 2.5 ? ? 3.6 3.6 v v f osc ? 16 mhz: f osc ? 32 mhz d001 2.3 2.5 ? ? 5.5 5.5 v v f osc ? 16 mhz: f osc ? 32 mhz d002* v dr ram data retention voltage (1) 1.5 ? ? v device in sleep mode d002* 1.7 ? ? v device in sleep mode d002a* v por power-on reset release voltage ?1.6? v d002b* v porr * power-on reset rearm voltage ?0.8? v d002b* ? 1.5 ? v d003 v adfvr fixed voltage reference voltage for adc -8 ? 6 % 1.024v, v dd ? 2.5v 2.048v, v dd ? 2.5v 4.096v, v dd ? 4.75v d003a v cdafvr fixed voltage reference voltage for comparator and dac -11 ? 7 % 1.024v, v dd ? 2.5v 2.048v, v dd ? 2.5v 4.096v, v dd ? 4.75v d004* s vdd v dd rise rate to ensure internal power-on reset signal 0.05 ? ? v/ms see section 7.1 ?power-on reset (por)? for details. * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data.
? 2011-2012 microchip technology inc. ds41441c-page 317 pic12(l)f1840 figure 30-4: por and por rearm with slow rising v dd v dd v por v porr v ss v ss npor (1) t por (3) por rearm note 1: when npor is low, the device is held in reset. 2: t por 1 ? s typical. 3: t vlow 2.7 ? s typical. t vlow (2)
pic12(l)f1840 ds41441c-page 318 ? 2011-2012 microchip technology inc. 30.2 dc characteristics: supply current (i dd ) pic12lf1840 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended pic12f1840 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. device characteristics min. typ? max. units conditions v dd note supply current (i dd ) (1, 2) d010 ? 5.0 12 ? a1.8 f osc = 32 khz lp oscillator -40c ? t a ? +85c ?7.4 25 ? a3.0 d010 ? 17 28 ? a 2.3 f osc = 32 khz lp oscillator -40c ? t a ? +85c ? 19 38 ? a 3.0 ? 22 45 ? a 5.0 d010a ? 5.0 21 ? a1.8f osc = 32 khz lp oscillator -40c ? t a ? +125c ?7.4 25 ? a3.0 d010a ? 17 60 ? a 2.3 f osc = 32 khz lp oscillator -40c ? t a ? +125c ? 19 70 ? a 3.0 ? 22 80 ? a 5.0 d011 ? 60 95 ? a1.8f osc = 1 mhz xt oscillator ?119 180 ? a3.0 d011 ? 110 200 ? a 2.3 f osc = 1 mhz xt oscillator ? 150 300 ? a 3.0 ? 183 360 ? a 5.0 d012 ? 165 240 ? a1.8f osc = 4 mhz xt oscillator ? 309 430 ? a3.0 d012 ? 240 400 ? a 2.3 f osc = 4 mhz xt oscillator ? 332 500 ? a 3.0 ? 392 600 ? a 5.0 d013 ? 34 120 ? a1.8f osc = 1 mhz external clock (ecm), medium-power mode ?69 200 ? a3.0 d013 ? 70 150 ? a 2.3 f osc = 1 mhz external clock (ecm), medium-power mode ? 105 210 ? a 3.0 ? 136 250 ? a 5.0 ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt disabled. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: 8 mhz internal oscillator with 4x pll enabled. 4: 8 mhz crystal oscillator with 4x pll enabled. 5: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be extended by the formula i r = v dd /2r ext (ma) with r ext in k ??
? 2011-2012 microchip technology inc. ds41441c-page 319 pic12(l)f1840 supply current (i dd ) (1, 2) d014 ? 118 210 ? a1.8f osc = 4 mhz external clock (ecm), medium-power mode ? 222 380 ? a3.0 d014 ? 172 250 ? a 2.3 f osc = 4 mhz external clock (ecm), medium-power mode ? 290 380 ? a 3.0 ? 350 480 ? a 5.0 d015 ? 6.5 20 ? a1.8f osc = 31 khz lfintosc -40c ? t a ? +85c ?9.0 31 ? a3.0 d015 ? 18 45 ? a 2.3 f osc = 31 khz lfintosc -40c ? t a ? +85c ? 24 50 ? a 3.0 ? 25 60 ? a 5.0 d016 ? 103 190 ? a1.8f osc = 500 khz mfintosc ? 124 220 ? a3.0 d016 ? 132 200 ? a 2.3 f osc = 500 khz mfintosc ? 165 250 ? a 3.0 ? 210 300 ? a 5.0 d017 ? 0.5 0.9 ma 1.8 f osc = 8 mhz hfintosc ?0.8 1.3 ma 3.0 d017 ? 0.7 0.9 ma 2.3 f osc = 8 mhz hfintosc ? 0.9 1.3 ma 3.0 ? 1.0 1.5 ma 5.0 d018 ? 0.7 1.2 ma 1.8 f osc = 16 mhz hfintosc ?1.2 1.8 ma 3.0 d018 ? 0.9 1.5 ma 2.3 f osc = 16 mhz hfintosc ? 1.2 2.0 ma 3.0 ? 1.3 2.1 ma 5.0 30.2 dc characteristics: supply current (i dd ) (continued) pic12lf1840 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended pic12f1840 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. device characteristics min. typ? max. units conditions v dd note ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt disabled. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: 8 mhz internal oscillator with 4x pll enabled. 4: 8 mhz crystal oscillator with 4x pll enabled. 5: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be extended by the formula i r = v dd /2r ext (ma) with r ext in k ??
pic12(l)f1840 ds41441c-page 320 ? 2011-2012 microchip technology inc. supply current (i dd ) (1, 2) d019 ? 1.3 3.0 ma 3.0 f osc = 32 mhz hfintosc (note 3) ?2.3 4.0 ma 3.6 d019 ? 2.2 3.8 ma 3.0 f osc = 32 mhz hfintosc (note 3) ? 2.4 4.1 ma 5.0 d020 ? 1.3 2.5 ma 3.0 f osc = 32 mhz hs oscillator (note 4) ?1.7 3.0 ma 3.6 d020 ? 1.4 2.5 ma 3.0 f osc = 32 mhz hs oscillator (note 4) ? 1.8 3.0 ma 5.0 d021 ? 185 300 ? a1.8f osc = 4 mhz extrc (note 5) ? 390 480 ? a3.0 d021 ? 290 400 ? a 2.3 f osc = 4 mhz extrc (note 5) ? 415 550 ? a 3.0 ? 495 600 ? a 5.0 30.2 dc characteristics: supply current (i dd ) (continued) pic12lf1840 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended pic12f1840 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. device characteristics min. typ? max. units conditions v dd note ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt disabled. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: 8 mhz internal oscillator with 4x pll enabled. 4: 8 mhz crystal oscillator with 4x pll enabled. 5: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be extended by the formula i r = v dd /2r ext (ma) with r ext in k ??
? 2011-2012 microchip technology inc. ds41441c-page 321 pic12(l)f1840 30.3 dc characteristics: power-down base current (i pd ) pic12lf1840 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended pic12f1840 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. device characteristics min. typ? max. +85c max. +125c units conditions v dd note power-down base current (i pd ) (2) d022 ? 0.02 1.0 8.0 ? a 1.8 wdt, bor, fvr and t1osc disabled, all peripherals inactive ? 0.03 2.0 9.0 ? a3.0 d022 ? 0.2 1.3 10 ? a 2.3 wdt, bor, fvr and t1osc disabled, all peripherals inactive, low-power regulator active vregpm = 1 ? 0.3 2.0 12 ? a 3.0 ? 0.5 6.0 15 ? a 5.0 d023 ? 0.5 6.0 14 ? a 1.8 wdt current (note 1) ?0.87.0 17 ? a3.0 d023 ? 0.5 6 15 ? a 2.3 wdt current vregpm = 1 (note 1) ? 0.8 7 20 ? a 3.0 ? 0.9 8 22 ? a 5.0 d023a ? 8.5 23 25 ? a 1.8 fvr current (note 1) ? 8.5 24 27 ? a3.0 d023a ? 18 26 30 ? a 2.3 fvr current vregpm = 0 (note 1) ? 19 27 37 ? a 3.0 ? 20 29 45 ? a 5.0 d024 ? 8.0 17 20 ? a 3.0 bor current (note 1) d024 ? 8.0 17 30 ? a 3.0 bor current vregpm = 1 (note 1) ? 9.0 20 40 ? a 5.0 d025 ? 0.3 5 9 ? a 1.8 t1osc current (note 1) ?0.5 9 12 ? a3.0 d025 ? 1.1 6 10 ? a 2.3 t1osc current vregpm = 1 (note 1) ? 1.3 9 20 ? a 3.0 ? 1.4 10 25 ? a 5.0 d026 ? 0.1 1.0 9 ? a 1.8 adc current (note 1, 3) no conversion in progress ?0.12.0 10 ? a3.0 d026 ? 0.2 3.0 10 ? a 2.3 adc current no conversion in progress vregpm = 1 (note 1, 3) ? 0.4 4.0 11 ? a 3.0 ? 0.5 6.0 16 ? a 5.0 * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwis e stated. these parameters are for design guidance only and are not tested. note 1: the peripheral current is the sum of the base i dd or i pd and the additional current consumed when this peripheral is enabled. the peripheral ? current can be determined by subtracting the base i dd or i pd current from this limit. max. values should be used when calculating total current consumption. 2: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v ss . 3: adc clock source is f rc .
pic12(l)f1840 ds41441c-page 322 ? 2011-2012 microchip technology inc. power-down base current (i pd ) (2) d026a* ? 250 ? ? ? a 1.8 adc current (note 1, 3) conversion in progress ?250 ? ? ? a3.0 d026a* ? 280 ? ? ? a 2.3 adc current conversion in progress vregpm = 1 (note 1, 3) ? 280 ? ? ? a 3.0 ? 280 ? ? ? a 5.0 d027 ? 3 12 15 ? a 1.8 cap sense, low power cpsrm = 0 , cpsrng = 01 (note 1) ? 4 15 18 ? a3.0 d027 ? 6.3 13 16 ? a 2.3 cap sense, low power cpsrm = 0 , cpsrng = 01 vregpm = 1 (note 1) ? 8.5 18 20 ? a 3.0 ? 12.8 23 25 ? a 5.0 d027a ? 6.0 15 20 ? a 1.8 cap sense, medium power cpsrm = 0 , cpsrng = 10 (note 1) ? 8.0 18 25 ? a3.0 d027a ? 9.5 20 25 ? a 2.3 cap sense, medium power cpsrm = 0 , cpsrng = 10 vregpm = 1 (note 1) ? 13 28 30 ? a 3.0 ? 17 32 35 ? a 5.0 d027b ? 15 35 40 ? a 1.8 cap sense, high power cpsrm = 0 , cpsrng = 11 (note 1) ?39 60 75 ? a3.0 d027b ? 20 40 45 ? a 2.3 cap sense, high power cpsrm = 0 , cpsrng = 11 vregpm = 1 (note 1) ? 42 68 80 ? a 3.0 ? 49 72 86 ? a 5.0 d028 ? 4.8 15 20 ? a 1.8 comparator, low power, cxsp = 0 (note 1) ? 4.9 17 23 ? a3.0 d028 ? 4.9 16 21 ? a 2.3 comparator, low power, cxsp = 0 vregpm = 1 (note 1) ? 5.0 17 23 ? a 3.0 ? 5.2 18 24 ? a 5.0 d028a ? 27 50 60 ? a 1.8 comparator, normal power, cxsp = 1 (note 1) ?28 55 70 ? a3.0 d028a ? 27 52 62 ? a 2.3 comparator, normal power, cxsp = 1 vregpm = 1 (note 1) ? 28 55 65 ? a 3.0 ? 29 57 75 ? a 5.0 30.3 dc characteristics: power-down base current (i pd ) (continued) pic12lf1840 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended pic12f1840 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. device characteristics min. typ? max. +85c max. +125c units conditions v dd note * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the peripheral current is the sum of the base i dd or i pd and the additional current consumed when this peripheral is enabled. the peripheral ? current can be determined by subtracting the base i dd or i pd current from this limit. max. values should be used when calculating total current consumption. 2: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v ss . 3: adc clock source is f rc .
? 2011-2012 microchip technology inc. ds41441c-page 323 pic12(l)f1840 30.4 dc characteristics: i/o ports dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. sym. characteristic min. typ? max. units conditions v il input low voltage i/o port: d030 with ttl buffer ? ? 0.8 v 4.5v ? v dd ? 5.5v d030a ? ? 0.15 v dd v1.8v ? v dd ? 4.5v d031 with schmitt trigger buffer ? ? 0.2 v dd v2.0v ? v dd ? 5.5v with i 2 c? levels ? ? 0.3 v dd v with smbus levels ? ? 0.8 v 2.7v ? v dd ? 5.5v d032 mclr , osc1 (rc mode) ? ? 0.2 v dd v (note 1) d033 osc1 (hs mode) ? ? 0.3 v dd v v ih input high voltage i/o port: d040 with ttl buffer 2.0 ? ? v 4.5v ? v dd ?? 5.5v d040a 0.25 v dd + 0.8 ??v1.8v ? v dd ? 4.5v d041 with schmitt trigger buffer 0.8 v dd ??v2.0v ? v dd ? 5.5v with i 2 c? levels 0.7 v dd ??v with smbus levels 2.1 ? ? v 2.7v ? v dd ? 5.5v d042 mclr 0.8 v dd ??v d043a osc1 (hs mode) 0.7 v dd ??v d043b osc1 (rc mode) 0.9 v dd ??vv dd > 2.0v (note 1) i il input leakage current (2) d060 i/o ports ? 5 125 na v ss ? v pin ? v dd , pin at high impedance, 85c ? 5 1000 na v ss ? v pin ? v dd , pin at high impedance, 125c d061 mclr (3) ? 50 200nav ss ? v pin ? v dd , pin at high impedance, 85c i pur weak pull-up current d070* 25 25 100 140 200 300 ? a ? a v dd = 3.3v, v pin = v ss v dd = 5.0v, v pin = v ss v ol output low voltage (4) d080 i/o ports ??0.6v i ol = 8 ma, v dd = 5v i ol = 6 ma, v dd = 3.3v i ol = 1.8 ma, v dd = 1.8v v oh output high voltage (4) d090 i/o ports v dd - 0.7 ? ? v i oh = 3.5 ma, v dd = 5v i oh = 3 ma, v dd = 3.3v i oh = 1 ma, v dd = 1.8v * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended to use an external clock in rc mode. 2: negative current is defined as current sourced by the pin. 3: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 4: including osc2 in clkout mode.
pic12(l)f1840 ds41441c-page 324 ? 2011-2012 microchip technology inc. capacitive loading specs on output pins d101* cosc2 osc2 pin ? ? 15 pf in xt, hs and lp modes when external clock is used to drive osc1 d101a* c io all i/o pins ? ? 50 pf 30.4 dc characteristics: i/o ports (continued) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. sym. characteristic min. typ? max. units conditions * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended to use an external clock in rc mode. 2: negative current is defined as current sourced by the pin. 3: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 4: including osc2 in clkout mode.
? 2011-2012 microchip technology inc. ds41441c-page 325 pic12(l)f1840 30.5 memory programming requirements dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. sym. characteristic min. typ? max. units conditions program memory programming specifications d110 v ihh voltage on mclr /v pp pin 8.0 ? 9.0 v (note 2) d111 i ddp supply current during programming ? ? 10 ma d112 v be v dd for bulk erase 2.7 ? v ddmax v d113 v pew v dd for write or row erase v ddmin ?v ddmax v d114 i pppgm current on mclr /v pp during erase/ write ?1.0?ma d115 i ddpgm current on v dd during erase/write ? 5.0 ?ma data eeprom memory d116 e d byte endurance 100k ? ? e/w -40 ? c to +85 ? c d117 v drw v dd for read/write v ddmin ?v ddmax v d118 t dew erase/write cycle time ? 4.0 5.0 ms d119 t retd characteristic retention ? 40 ? year provided no other specifications are violated d120 t ref number of total erase/write cycles before refresh 1m 10m ? e/w -40c to +85c program flash memory d121 e p cell endurance 10k ? ? e/w -40 ? c to +85 ? c ( note 1 ) d122 v prw v dd for read/write v ddmin ?v ddmax v d123 t iw self-timed write cycle time ? 2 2.5 ms d124 t retd characteristic retention ? 40 ? year provided no other specifications are violated ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: self-write and block erase. 2: required only if single-suppl y programming is disabled.
pic12(l)f1840 ds41441c-page 326 ? 2011-2012 microchip technology inc. 30.6 thermal considerations standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +125c param no. sym. characteristic typ. units conditions th01 ? ja thermal resistance junction to ambient 56.7 ? c/w 8-pin dfn package 89.3 ? c/w 8-pin pdip package 149.5 ? c/w 8-pin soic package th02 ? jc thermal resistance junction to case 9.0 ? c/w 8-pin dfn package 43.1 ? c/w 8-pin pdip package 39.9 ? c/w 8-pin soic package th03 t jmax maximum junction temperature 150 ? c th04 pd power dissipation ? w pd = p internal + p i / o th05 p internal internal power dissipation ? w p internal = i dd x v dd (1) th06 p i / o i/o power dissipation ? w p i / o = ? (i ol * v ol ) + ? (i oh * (v dd - v oh )) th07 p der derated power ? w p der = pd max (t j - t a )/ ? ja (2) note 1: i dd is current to run the chip alone without driving any load on the output pins. 2: t a = ambient temperature, t j = junction temperature.
? 2011-2012 microchip technology inc. ds41441c-page 327 pic12(l)f1840 30.7 timing parameter symbology the timing parameter symbols have been created with one of the following formats: figure 30-5: load conditions 1. tpps2pps 2. tpps t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdix sc sckx do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (high-impedance) v valid l low z high-impedance v ss c l legend: c l = 50 pf for all pins, 15 pf for osc2 output load condition pin
pic12(l)f1840 ds41441c-page 328 ? 2011-2012 microchip technology inc. 30.8 ac characteristics: pic12(l)f1840-i/e figure 30-6: clock timing table 30-1: clock oscillator timing requirements standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +125c param no. sym. characteristic min. typ? max. units conditions os01 f osc external clkin frequency (1) dc ? 0.5 mhz external clock (ecl) dc ? 4 mhz external clock (ecm) dc ? 32 mhz external clock (ech) oscillator frequency (1) ? 32.768 ? khz lp oscillator 0.1 ? 4 mhz xt oscillator 1 ? 4 mhz hs oscillator 1 ? 20 mhz hs oscillator, v dd > 2.7v dc ? 4 mhz rc oscillator, v dd > 2.0v os02 t osc external clkin period (1) 27 ? ?? s lp oscillator 250 ? ? ns xt oscillator 50 ? ? ns hs oscillator 50 ? ? ns external clock (ec) oscillator period (1) ? 30.5 ? ? s lp oscillator 250 ? 10,000 ns xt oscillator 50 ? 1,000 ns hs oscillator 250 ? ? ns rc oscillator os03 t cy instruction cycle time (1) 200 t cy dc ns t cy = 4/f osc os04* tosh, tosl external clkin high, external clkin low 2?? ? s lp oscillator 100 ? ? ns xt oscillator 20 ? ? ns hs oscillator os05* tosr, tosf external clkin rise, external clkin fall 0 ? ? ns lp oscillator 0 ? ? ns xt oscillator 0 ? ? ns hs oscillator * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise st ated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. all devices are tested to operate at ?min? values wi th an external clock applied to osc1 pin. when an external clock input is used, the ?max? cycle time limit is ?dc? (no clock) for all devices. osc1/clkin osc2/clkout q4 q1 q2 q3 q4 q1 os02 os03 os04 os04 osc2/clkout (lp,xt,hs modes) (clkout mode)
? 2011-2012 microchip technology inc. ds41441c-page 329 pic12(l)f1840 table 30-2: oscillator parameters table 30-3: pll clock timing specifications (v dd = 2.7v to 5.5v) standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param no. sym. characteristic freq. tolerance min. typ? max. units conditions os08 hf osc internal calibrated hfintosc frequency (note 1) ? 2% ? 16.0 ? mhz 0c ? t a ? +60c, v dd ? 2.5v ? 3% ? 16.0 ? mhz 60c ? t a ? +85c, v dd ? 2.5v ? 5% ? 16.0 ? mhz -40c ? t a ? +125c os08a mf osc internal calibrated mfintosc frequency (note 1) ? 2% ? 500 ? mhz 0c ? t a ? +60c, v dd ? 2.5v ? 3% ? 500 ? khz 60c ? t a ? +85c, v dd ? 2.5v ? 5% ? 500 ? khz -40c ? t a ? +125c os09 lf osc internal lfintosc frequency ? ? 31 ? khz (note 2) os10* t iosc st hfintosc wake-up from sleep start-up time mfintosc wake-up from sleep start-up time ? ? ? ? ? ? 5 ? 20 8 ? 30 ? s ? s * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise st ated. these parameters are for design guidance only and are not tested. note 1: to ensure these oscillator frequency tolerances, v dd and v ss must be capacitively decoupled as close to the device as possible. 0.1 ? f and 0.01 ? f values in parallel are recommended. 2: see figure 31-65 and figure 31-66 , lfintosc frequency characteristics over v dd and temperature. param no. sym. characteristic min. typ? max. units conditions f10 f osc oscillator frequency range 4 ? 8 mhz f11 f sys on-chip vco system frequency 16 ? 32 mhz f12 t rc pll start-up time (lock time) ? ? 2 ms f13* ? clk clkout stability (jitter) -0.25% ? +0.25% % * these parameters are characterized but not tested. ? data in ?typ? column is at 3v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested.
pic12(l)f1840 ds41441c-page 330 ? 2011-2012 microchip technology inc. figure 30-7: clkout and i/o timing table 30-4: clkout and i/o timing parameters standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param no. sym. characteristic min. typ? max. units conditions os11 tosh2ckl f osc ? to clkout ? (note 1) ??70nsv dd = 3.3-5.0v os12 tosh2ckh f osc ? to clkout ? (note 1) ??72nsv dd = 3.3-5.0v os13 tckl2iov clkout ? to port out valid (note 1) ??20ns os14 tiov2ckh port input valid before clkout ?? (note 1) t osc + 200 ns ? ? ns os15 tosh2iov fosc ? (q1 cycle) to port out valid ? 50 70* ns v dd = 3.3-5.0v os16 tosh2ioi fosc ? (q2 cycle) to port input invalid (i/o in setup time) 50 ? ? ns v dd = 3.3-5.0v os17 tiov2osh port input valid to fosc ?? (q2 cycle) (i/o in setup time) 20 ? ? ns os18* tior port output rise time ? ? 40 15 72 32 ns v dd = 1.8v v dd = 3.3-5.0v os19* tiof port output fall time ? ? 28 15 55 30 ns v dd = 1.8v v dd = 3.3-5.0v os20* tinp int pin input high or low time 25 ? ? ns os21* tioc interrupt-on-change new input level time 25 ? ? ns * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25 ? c unless otherwise stated. note 1: measurements are taken in rc mode where clkout output is 4 x t osc . f osc clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 os11 os19 os13 os15 os18, os19 os20 os21 os17 os16 os14 os12 os18 old value new value write fetch read execute cycle
? 2011-2012 microchip technology inc. ds41441c-page 331 pic12(l)f1840 figure 30-8: reset, watchdog timer, os cillator start-up timer and power-up timer timing figure 30-9: brown-out rese t timing and characteristics v dd mclr internal por pwrt time-out osc start-up time internal reset (1) watchdog timer 33 32 30 31 34 i/o pins 34 note 1: asserted low. reset (1) v bor v dd (device in brown-out reset) (device not in brown-out reset) 33 (1) note 1: 64 ms delay only if pwrte bit in the configuration words is programmed to ? 0 ?. 2 ms delay if pwrte = 0 and vregen = 1 . reset (due to bor) v bor and v hyst 37
pic12(l)f1840 ds41441c-page 332 ? 2011-2012 microchip technology inc. table 30-5: reset, watchdog timer, oscill ator start-up timer, power-up timer and brown-out reset parameters standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param no. sym. characteristic min. typ? max. units conditions 30 t mc lmclr pulse width (low) 2 ? ? ? s 31 t wdtlp low-power watchdog timer time-out period 10 16 27 ms v dd = 3.3v-5v, 1:16 prescaler used 32 t ost oscillator start-up timer period (note 1) ? 1024 ? tosc 33* t pwrt power-up timer period, pwrte = 0 40 65 140 ms 34* t ioz i/o high-impedance from mclr low or watchdog timer reset ??2.0 ? s 35 v bor brown-out reset voltage (note 2) 2.55 2.35 1.80 2.70 2.45 1.90 2.85 2.58 2.00 v v v borv = 0 , pic12(l)f1840 borv = 1 , pic12f1840 pic12lf1840 37* v hyst brown-out reset hysteresis 0 25 60 mv -40c to +85c 38* t bordc brown-out reset dc response time 1335 ? sv dd ? v bor * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: by design, the oscillator start-up timer (ost) counts the first 1024 cycles, independent of frequency. 2: to ensure these voltage tolerances, v dd and v ss must be capacitively decoupled as close to the device as possible. 0.1 ? f and 0.01 ? f values in parallel are recommended.
? 2011-2012 microchip technology inc. ds41441c-page 333 pic12(l)f1840 figure 30-10: timer0 and timer1 external clock timings table 30-6: timer0 and timer1 external clock requirements standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param no. sym. characteristic min. typ? max. units conditions 40* t t 0h t0cki high pulse width no prescaler 0.5 t cy + 20 ? ? ns with prescaler 10 ? ? ns 41* t t 0l t0cki low pulse width no prescaler 0.5 t cy + 20 ? ? ns with prescaler 10 ? ? ns 42* t t 0p t0cki period greater of: 20 or t cy + 40 n ? ? ns n = prescale value 45* t t 1h t1cki high time synchronous, no prescaler 0.5 t cy + 20 ? ? ns synchronous, with prescaler 15 ? ? ns asynchronous 30 ? ? ns 46* t t 1l t1cki low time synchronous, no prescaler 0.5 t cy + 20 ? ? ns synchronous, with prescaler 15 ? ? ns asynchronous 30 ? ? ns 47* t t 1p t1cki input period synchronous greater of: 30 or t cy + 40 n ? ? ns n = prescale value asynchronous 60 ? ? ns 48 f t 1 timer1 oscillator input frequency range (oscillator enabled by setting bit t1oscen) 32.4 32.768 33.1 khz 49* tckez tmr 1 delay from external clock edge to timer increment 2 t osc ?7 t osc ? timers in sync mode * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise st ated. these parameters are for design guidance only and are not tested. t0cki t1cki 40 41 42 45 46 47 49 tmr0 or tmr1
pic12(l)f1840 ds41441c-page 334 ? 2011-2012 microchip technology inc. figure 30-11: capture/com pare/pwm timings (ccp) table 30-7: capture/compare/pwm requirements (ccp) table 30-8: analog-to-digital converter (adc) characteristics (1,2,3) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +125c param no. sym. characteristic min. typ? max. units conditions cc01* tccl ccp input low time no prescaler 0.5t cy + 20 ? ? ns with prescaler 20 ? ? ns cc02* tcch ccp input high time no prescaler 0.5t cy + 20 ? ? ns with prescaler 20 ? ? ns cc03* tccp ccp input period 3t cy + 40 n ? ? ns n = prescale value * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. standard operating conditions (unless otherwise stated) operating temperature t a ?? 25c param no. sym. characteristic min. typ? max. units conditions ad01 n r resolution ? ? 10 bit ad02 e il integral error ? 1 1.7 lsb v ref = 3.0v ad03 e dl differential error ? 1 1 lsb no missing codes v ref = 3.0v ad04 e off offset error ? 1 2.5 lsb v ref = 3.0v ad05 e gn gain error ? 1 2.0 lsb v ref = 3.0v ad06 v ref reference voltage (note 4 )1.8?v dd vv ref = (v ref + minus v ref -) ad07 v ain full-scale range v ss ?v ref v ad08 z ain recommended impedance of analog voltage source ?? 10k ? can go higher if external 0.01 ? f capacitor is present on input pin. * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise st ated. these parameters are for design guidance only and are not tested. note 1: total absolute error includes integral, differential, offset and gain errors. 2: the adc conversion result never decreases with an increase in the input voltage and has no missing codes. 3: adc v ref is from external v ref , v dd pin or fvr, whichever is selected as reference input. 4: adc reference voltage (ref+) is the selected reference input, v ref + pin, v dd pin or the fvr buffer1. when the fvr is selected as the reference input, the fvr buffer1 output selection must be 2.048v or 4.096v (adfvr<1:0> = 1x ). note: refer to figure 30-5 for load conditions. (capture mode) cc01 cc02 cc03 ccp
? 2011-2012 microchip technology inc. ds41441c-page 335 pic12(l)f1840 table 30-9: adc conversion requirements figure 30-12: adc conversion timing (normal mode) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +125c param no. sym. characteristic min. typ? max. units conditions ad130* t ad adc clock period 1.0 ? 9.0 ? sf osc -based adc internal rc oscillator period 1.0 2.0 6.0 ? s adcs<2:0> = x11 (adc frc mode) ad131 t cnv conversion time (not including acquisition time) (note 1) ?11?t ad set go/done bit to conversion complete ad132* t acq acquisition time ? 5.0 ? ? s * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the adres register may be read on the following t cy cycle. ad131 ad130 bsf adcon0, go q4 adc clk adc data adres adif go sample old_data sampling stopped done new_data 765 3210 note 1: if the adc clock source is selected as rc, a time of t cy is added before the adc clock starts. this allows the sleep instruction to be executed. 1 t cy 4 ad134 (t osc /2 (1) ) 1 t cy ad132
pic12(l)f1840 ds41441c-page 336 ? 2011-2012 microchip technology inc. figure 30-13: adc conversion timing (sleep mode) ad132 ad131 ad130 bsf adcon0, go q4 adc clk adc data adres adif go sample old_data sampling stopped done new_data 7 5 3210 note 1: if the adc clock source is selected as rc, a time of t cy is added before the adc clock starts. this allows the sleep instruction to be executed. ad134 4 6 1 t cy (t osc /2 + t cy (1) ) 1 t cy
? 2011-2012 microchip technology inc. ds41441c-page 337 pic12(l)f1840 table 30-10: comparator specifications table 30-11: digital-to-analog conv erter (dac) specifications operating conditions: 1.8v < v dd < 5.5v, -40c < t a < +125c (unless otherwise stated). param no. sym. characteristics min. typ. max. units comments cm01 v ioff input offset voltage ? 7.5 60 mv cxsp = 1 v icm = v dd /2 cm02 v icm input common mode voltage 0 ? v dd v cm03 cmrr common mode rejection ratio ? 50 ? db cm04a t resp (1) response time rising edge ? 400 800 ns cxsp = 1 cm04b response time falling edge ? 200 400 ns cxsp = 1 cm04c response time rising edge ? 1200 ? ns cxsp = 0 cm04d response time falling edge ? 550 ? ns cxsp = 0 cm05 t mc 2 ov comparator mode change to output valid* ??10 ? s cm06 c hyster comparator hysteresis ? 45 ? mv cxhys = 1 , cxsp = 1 (note 2) * these parameters are characterized but not tested. note 1: response time measured with one comparator input at v dd /2, while the other input transitions from v ss to v dd . 2: comparator hysteresis is available when the cxhys bit of the cmxcon0 register is enabled. operating conditions: 1.8v < v dd < 5.5v, -40c < t a < +125c (unless otherwise stated). param no. sym. characteristics min. typ. max. units comments dac01 c lsb step size ? v dd /32 ? v dac02 c acc absolute accuracy ? ? ? 1/2 lsb v dd = 3.0v, t a = +25c dac03 c r unit resistor value (r) ? 5k ? ? dac04* c st settling time (note 1) ??10 ? s * parameter(s) characterized but not tested. note 1: settling time measured while dacr<4:0> transitions from ? 0000 ? to ? 1111 ?.
pic12(l)f1840 ds41441c-page 338 ? 2011-2012 microchip technology inc. figure 30-14: usart synchronous transmission (master/slave) timing table 30-12: usart synchronous tran smission requirements figure 30-15: usart synchrono us receive (master/slave) timing table 30-13: usart synchronous rece ive requirements standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param. no. symbol characteristic min. max. units conditions us120 t ck h2 dt v sync xmit (master and slave) clock high to data-out valid 3.0-5.5v ? 80 ns 1.8-5.5v ? 100 ns us121 t ckrf clock out rise time and fall time (master mode) 3.0-5.5v ? 45 ns 1.8-5.5v ? 50 ns us122 t dtrf data-out rise time and fall time 3.0-5.5v ? 45 ns 1.8-5.5v ? 50 ns standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param. no. symbol characteristic min. max. units conditions us125 t dt v2 ckl sync rcv (master and slave) data-hold before ck ? (dt hold time) 10 ? ns us126 t ck l2 dtl data-hold after ck ? (dt hold time) 15 ? ns note: refer to figure 30-5 for load conditions. us121 us121 us120 us122 ck dt note: refer to figure 30-5 for load conditions. us125 us126 ck dt
? 2011-2012 microchip technology inc. ds41441c-page 339 pic12(l)f1840 figure 30-16: spi master mode timing (cke = 0 , smp = 0 ) figure 30-17: spi master mode timing (cke = 1 , smp = 1 ) ss x sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix sp70 sp71 sp72 sp73 sp74 sp75, sp76 sp78 sp79 sp80 sp79 sp78 msb lsb bit 6 - - - - - -1 msb in lsb in bit 6 - - - -1 note: refer to figure 30-5 for load conditions. ss x sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix sp81 sp71 sp72 sp74 sp75, sp76 sp78 sp80 msb sp79 sp73 msb in bit 6 - - - - - -1 lsb in bit 6 - - - -1 lsb note: refer to figure 30-5 for load conditions.
pic12(l)f1840 ds41441c-page 340 ? 2011-2012 microchip technology inc. figure 30-18: spi slav e mode timing (cke = 0 ) figure 30-19: spi slav e mode timing (cke = 1 ) ss x sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix sp70 sp71 sp72 sp73 sp74 sp75, sp76 sp77 sp78 sp79 sp80 sp79 sp78 msb lsb bit 6 - - - - - -1 msb in bit 6 - - - -1 lsb in sp83 note: refer to figure 30-5 for load conditions. ss x sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix sp70 sp71 sp72 sp82 sp74 sp75, sp76 msb bit 6 - - - - - -1 lsb sp77 msb in bit 6 - - - -1 lsb in sp80 sp83 note: refer to figure 30-5 for load conditions.
? 2011-2012 microchip technology inc. ds41441c-page 341 pic12(l)f1840 table 30-14: spi mode requirements param no. symbol characteristic min. typ? max. units conditions sp70* t ss l2 sc h, t ss l2 sc l ss ? to sck ? or sck ? input t cy ??ns sp71* t sc h sck input high time (slave mode) t cy + 20 ? ? ns sp72* t sc l sck input low time (slave mode) t cy + 20 ? ? ns sp73* t di v2 sc h, t di v2 sc l setup time of sdi data input to sck edge 100 ? ? ns sp74* t sc h2 di l, t sc l2 di l hold time of sdi data input to sck edge 100 ? ? ns sp75* t do r sdo data output rise time 3.0-5.5v ? 10 25 ns 1.8-5.5v ? 25 50 ns sp76* t do f sdo data output fall time ? 10 25 ns sp77* t ss h2 do zss ? to sdo output high-impedance 10 ? 50 ns sp78* t sc r sck output rise time (master mode) 3.0-5.5v ? 10 25 ns 1.8-5.5v ? 25 50 ns sp79* t sc f sck output fall time (master mode) ? 10 25 ns sp80* t sc h2 do v, t sc l2 do v sdo data output valid after sck edge 3.0-5.5v ? ? 50 ns 1.8-5.5v ? ? 145 ns sp81* t do v2 sc h, t do v2 sc l sdo data output setup to sck edge tcy ? ? ns sp82* t ss l2 do v sdo data output valid after ss ? edge ? ? 50 ns sp83* t sc h2 ss h, t sc l2 ss h ss ?? after sck edge 1.5t cy + 40 ? ? ns * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested.
pic12(l)f1840 ds41441c-page 342 ? 2011-2012 microchip technology inc. figure 30-20: i 2 c? bus start/stop bits timing note : refer to figure 30-5 for load conditions. sp91 sp92 sp93 sclx sdax start condition stop condition sp90 table 30-15: i 2 c? bus start/stop bits requirements param. no. symbol characteristic min. typ. max. units conditions sp90* t su : sta start condition 100 khz mode 4700 ? ? ns only relevant for repeated start condition setup time 400 khz mode 600 ? ? sp91* t hd : sta start condition 100 khz mode 4000 ? ? ns after this period, the first clock pulse is generated hold time 400 khz mode 600 ? ? sp92* t su : sto stop condition 100 khz mode 4700 ? ? ns setup time 400 khz mode 600 ? ? sp93* t hd : sto stop condition 100 khz mode 4000 ? ? ns hold time 400 khz mode 600 ? ? * these parameters are characterized but not tested.
? 2011-2012 microchip technology inc. ds41441c-page 343 pic12(l)f1840 figure 30-21: i 2 c? bus data timing i note: refer to figure 30-5 for load conditions. sp90 sp91 sp92 sp100 sp101 sp103 sp106 sp107 sp109 sp109 sp110 sp102 sclx sdax in sdax out table 30-16: i 2 c? bus data requirements param. no. symbol characteristic min. max. units conditions sp100* t high clock high time 100 khz mode 4.0 ? ? s device must operate at a minimum of 1.5 mhz 400 khz mode 0.6 ? ? s device must operate at a minimum of 10 mhz ssp module 1.5t cy ?? sp101* t low clock low time 100 khz mode 4.7 ? ? s device must operate at a minimum of 1.5 mhz 400 khz mode 1.3 ? ? s device must operate at a minimum of 10 mhz ssp module 1.5t cy ?? sp102* t r sda and scl rise time 100 khz mode ? 1000 ns 400 khz mode 20 + 0.1c b 300 ns c b is specified to be from 10-400 pf sp103* t f sda and scl fall time 100 khz mode ? 250 ns 400 khz mode 20 + 0.1c b 250 ns c b is specified to be from 10-400 pf sp106* t hd : dat data input hold time 100 khz mode 0 ? ns 400 khz mode 0 0.9 ? s sp107* t su : dat data input setup time 100 khz mode 250 ? ns (note 2) 400 khz mode 100 ? ns sp109* t aa output valid from clock 100 khz mode ? 3500 ns (note 1) 400 khz mode ? ? ns sp110* t buf bus free time 100 khz mode 4.7 ? ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? ? s sp111 c b bus capacitive loading ? 400 pf * these parameters are characterized but not tested. note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast mode (400 khz) i 2 c? bus device can be used in a standard mode (100 khz) i 2 c bus system, but the requirement t su : dat ?? 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max. + t su : dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification), before the scl line is released.
pic12(l)f1840 ds41441c-page 344 ? 2011-2012 microchip technology inc. table 30-17: cap sense os cillator specifications figure 30-22: cap sense oscillator param. no. symbol characteristic min. typ? max. units conditions cs01* i src current source high ? -8 ? ? a (note 1) medium ? -1.5 ? ? a (note 1) low ? -0.3 ? ? a (note 1) cs02* i snk current sink high ? 7.5 ? ? a (note 1) medium ? 1.5 ? ? a (note 1) low ? 0.25 ? ? a (note 1) cs03* vc th cap threshold ? 0.8 ? v cs04* vc tl cap threshold ? 0.4 ? v cs05* vc hyst cap hysteresis (v cth - v ctl ) high ? 525 ? mv medium ? 375 ? mv low ? 300 ? mv * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: see figure 31-67 , figure 31-68 and figure 31-69 , cap sense current sink/source characteristics. i src vc th vc tl i snk enabled enabled
? 2011-2012 microchip technology inc. ds41441c-page 345 pic12(l)f1840 31.0 dc and ac characteristics graphs and charts the graphs and tables provided in this section are for design guidance and are not tested . in some graphs or tables, the data presented are outside specified operating range (i.e., outside specified v dd range). this is for information only and devices are ensured to operate properly only within the specified range. ? typical? represents the mean of the distribution at 25 ? c. ?maximum?, ?max.?, ?minimum? or ?min.? represents (mean + 3 ? ) or (mean - 3 ? ) respectively, where ? is a standard deviation, over each temper- ature range. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
pic12(l)f1840 ds41441c-page 346 ? 2011-2012 microchip technology inc. figure 31-1: i dd , lp oscillator, f osc = 32 khz, pic12lf1840 only figure 31-2: i dd , lp oscillator, f osc = 32 khz, pic12f1840 only typical max. 0 5 10 15 20 25 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd ( a) v dd (v) max: 85c + 3 typical: 25c typical max. 0 5 10 15 20 25 30 35 40 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd ( a) v dd (v) max: 85c + 3 typical: 25c
? 2011-2012 microchip technology inc. ds41441c-page 347 pic12(l)f1840 figure 31-3: i dd typical, xt and extrc oscillator, pic12lf1840 only figure 31-4: i dd maximum, xt and extrc oscillator, pic12lf1840 only 4 mhz extrc 4 mhz xt 1 mhz xt 0 50 100 150 200 250 300 350 400 450 500 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd ( a) v dd (v) typical: 25c 4 mhz extrc 4 mhz xt 1 mhz xt 0 100 200 300 400 500 600 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd ( a) v dd (v) max: 85c + 3
pic12(l)f1840 ds41441c-page 348 ? 2011-2012 microchip technology inc. figure 31-5: i dd typical, xt and extrc oscillator, pic12f1840 only figure 31-6: i dd maximum, xt and extrc oscillator, pic12f1840 only 4 mhz extrc 4 mhz xt 1 mhz xt 0 100 200 300 400 500 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd ( a) v dd (v) typical: 25c 4 mhz extrc 4 mhz xt 1 mhz xt 0 100 200 300 400 500 600 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd ( a) v dd (v) max: 85c + 3
? 2011-2012 microchip technology inc. ds41441c-page 349 pic12(l)f1840 figure 31-7: i dd , external clock (ecl), low-power mode, f osc = 32 khz, pic12lf1840 only figure 31-8: i dd , external clock (ecl), low-power mode, f osc = 32 khz, pic12f1840 only typical max. 0 2 4 6 8 10 12 14 16 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd ( a) v dd (v) max: 85c + 3 typical: 25c typical max. 0 5 10 15 20 25 30 35 40 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd (a) v dd (v) max: 85c + 3 typical: 25c
pic12(l)f1840 ds41441c-page 350 ? 2011-2012 microchip technology inc. figure 31-9: i dd , external clock (ecl), low-power mode, f osc = 500 khz, pic12lf1840 only figure 31-10: i dd , external clock (ecl), low-power mode, f osc = 500 khz, pic12f1840 only max. typical 0 10 20 30 40 50 60 70 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd ( a) v dd (v) max: 85c + 3 typical: 25c typical max. 0 10 20 30 40 50 60 70 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd ( a) v dd (v) max: 85c + 3 typical: 25c
? 2011-2012 microchip technology inc. ds41441c-page 351 pic12(l)f1840 figure 31-11: i dd typical, external clock (ecm), medium-power mode, pic12lf1840 only figure 31-12: i dd maximum, external clock (ecm), medium-power mode, pic12lf1840 only 4 mhz 1 mhz 0 50 100 150 200 250 300 350 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd ( a) v dd (v) typical: 25c 4 mhz 1 mhz 0 50 100 150 200 250 300 350 400 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd ( a) v dd (v) max: 85c + 3
pic12(l)f1840 ds41441c-page 352 ? 2011-2012 microchip technology inc. figure 31-13: i dd typical, external clock (ecm), medium-power mode, pic12f1840 only figure 31-14: i dd maximum, external clock (ecm), medium-power mode, pic12f1840 only 4 mhz 1 mhz 0 50 100 150 200 250 300 350 400 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd ( a) v dd (v) typical: 25c 4 mhz 1 mhz 0 50 100 150 200 250 300 350 400 450 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd ( a) v dd (v) max: 85c + 3
? 2011-2012 microchip technology inc. ds41441c-page 353 pic12(l)f1840 figure 31-15: i dd typical, external clock (ech), high-power mode, pic12lf1840 only figure 31-16: i dd maximum, external clock (ech), high-power mode, pic12lf1840 only 32 mhz 16 mhz 8 mhz 0.0 0.5 1.0 1.5 2.0 2.5 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd (ma) v dd (v) typical: 25c 32 mhz 16 mhz 8 mhz 0.0 0.5 1.0 1.5 2.0 2.5 3.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd (ma) v dd (v) max: 85c + 3
pic12(l)f1840 ds41441c-page 354 ? 2011-2012 microchip technology inc. figure 31-17: i dd typical, external clock (ech), high-power mode, pic12f1840 only figure 31-18: i dd maximum, external clock (ech), high-power mode, pic12f1840 only 32 mhz 16 mhz 8 mhz 0.0 0.5 1.0 1.5 2.0 2.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd (ma) v dd (v) typical: 25c 32 mhz 16 mhz 8 mhz 0.0 0.5 1.0 1.5 2.0 2.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd (ma) v dd (v) max: 85c + 3
? 2011-2012 microchip technology inc. ds41441c-page 355 pic12(l)f1840 figure 31-19: i dd , lfintosc, f osc = 31 khz, pic12lf1840 only figure 31-20: i dd , lfintosc, f osc = 31 khz, pic12f1840 only typical max. 0 5 10 15 20 25 30 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd (a) v dd (v) max: 85c + 3 typical: 25c typical max. 0 5 10 15 20 25 30 35 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd ( a) v dd (v) max: 85c + 3 typical: 25c
pic12(l)f1840 ds41441c-page 356 ? 2011-2012 microchip technology inc. figure 31-21: i dd , mfintosc, f osc = 500 khz, pic12lf1840 only figure 31-22: i dd , mfintosc, f osc = 500 khz, pic12f1840 only typical max. 0 20 40 60 80 100 120 140 160 180 200 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd ( a) v dd (v) max: 85c + 3 typical: 25c typical max. 0 50 100 150 200 250 300 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd ( a) v dd (v) max: 85c + 3 typical: 25c
? 2011-2012 microchip technology inc. ds41441c-page 357 pic12(l)f1840 figure 31-23: i dd typical, hfintosc, pic12lf1840 only figure 31-24: i dd maximum, hfintosc, pic12lf1840 only 32 mhz (4x pll) 16 mhz 8 mhz 4 mhz 0.0 0.5 1.0 1.5 2.0 2.5 3.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd (ma) v dd (v) typical: 25c 32 mhz (4x pll) 16 mhz 8 mhz 4 mhz 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd (ma) v dd (v) max: 85c + 3
pic12(l)f1840 ds41441c-page 358 ? 2011-2012 microchip technology inc. figure 31-25: i dd typical, hfintosc, pic12f1840 only figure 31-26: i dd maximum, hfintosc, pic12f1840 only 32 mhz (4x pll) 16 mhz 8 mhz 4 mhz 0.0 0.5 1.0 1.5 2.0 2.5 3.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd (ma) v dd (v) typical: 25c 32 mhz (4x pll) 16 mhz 8 mhz 4 mhz 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd (ma) v dd (v) max: 85c + 3
? 2011-2012 microchip technology inc. ds41441c-page 359 pic12(l)f1840 figure 31-27: i dd typical, hs oscillator, pic12lf1840 only figure 31-28: i dd maximum, hs oscillator, pic12lf1840 only 32 mhz 8 mhz 4 mhz 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd (ma) v dd (v) typical: 25c 32 mhz 8 mhz 4 mhz 0.0 0.5 1.0 1.5 2.0 2.5 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd (ma) v dd (v) max: 85c + 3
pic12(l)f1840 ds41441c-page 360 ? 2011-2012 microchip technology inc. figure 31-29: i dd typical, hs oscillator, pic12f1840 only figure 31-30: i dd maximum, hs oscillator, pic12f1840 only 32 mhz 8 mhz 4 mhz 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd (ma) v dd (v) typical: 25c 32 mhz 8 mhz 4 mhz 0.0 0.5 1.0 1.5 2.0 2.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd (ma) v dd (v) max: 85c + 3
? 2011-2012 microchip technology inc. ds41441c-page 361 pic12(l)f1840 figure 31-31: i pd base, sleep mode, pic12lf1840 only figure 31-32: i pd base, low-power sleep mode, vregpm = 1 , pic12f1840 only 450 m85 c3 max. 250 300 350 400 450 d (na) max: 85c + 3 typical: 25c typical 0 50 100 150 200 250 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i pd (na) 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 v dd (v) max. 600 max. 300 400 500 600 p d (na) max: 85c + 3 typical: 25c typical 0 100 200 300 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd (na) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v)
pic12(l)f1840 ds41441c-page 362 ? 2011-2012 microchip technology inc. figure 31-33: i pd , watchdog timer (wdt), pic12lf1840 only figure 31-34: i pd , watchdog timer (wdt), pic12f1840 only 1.4 typical max. 0.6 0.8 1.0 1.2 1.4 i pd (a) max: 85c + 3 typical: 25c typical 0.0 0.2 0.4 0.6 08 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i pd ( a 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 v dd (v) 1.2 typical max. 0.6 0.8 1.0 1.2 i pd ( a) max: 85c + 3 typical: 25c typical 0.0 0.2 0.4 0.6 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( a 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v)
? 2011-2012 microchip technology inc. ds41441c-page 363 pic12(l)f1840 figure 31-35: i pd , fixed voltage reference (fvr), pic12lf1840 only figure 31-36: i pd , fixed voltage reference (fvr), pic12f1840 only max. 25 typical max. 10 15 20 25 i pd ( a) 0 5 10 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i pd ( a max: 85c + 3 typical: 25c 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 v dd (v) 30 typical max. 15 20 25 30 i pd ( a) 0 5 10 15 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( max: 85c + 3 typical: 25c 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v)
pic12(l)f1840 ds41441c-page 364 ? 2011-2012 microchip technology inc. figure 31-37: i pd , brown-out reset (bor), borv = 1 , pic12lf1840 only figure 31-38: i pd , brown-out reset (bor), borv = 1 , pic12f1840 only 12 typical max. 6 8 10 12 d ( a) max: 85c + 3 typical: 25c 0 2 4 6 16 18 20 22 24 26 28 30 32 34 36 38 i pd ( a) 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 v dd (v) max 14 ma 85 c+3 typical max. 6 8 10 12 14 i pd ( a) max: 85c + 3 typical: 25c 0 2 4 6 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( a ) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v)
? 2011-2012 microchip technology inc. ds41441c-page 365 pic12(l)f1840 figure 31-39: i pd , timer1 oscillator, f osc = 32 khz, pic12lf1840 only figure 31-40: i pd , timer1 oscillator, f osc = 32 khz, pic12f1840 only 6.0 t yp ical max. 3.0 4.0 5.0 6.0 i pd ( a) max: 85c + 3 typical: 25c typical 0.0 1.0 2.0 3.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i pd ( a 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 v dd (v) 12 typical max. 6 8 10 12 i pd ( a) max: 85c + 3 typical: 25c typical 0 2 4 6 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v)
pic12(l)f1840 ds41441c-page 366 ? 2011-2012 microchip technology inc. figure 31-41: v oh vs. i oh over temperature, v dd = 5.5v, pic12f1840 only figure 31-42: v ol vs. i ol over temperature, v dd = 5.5v, pic12f1840 only -40c typical 125c 0 1 2 3 4 5 6 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 v oh (v) i oh (ma) graph represents 3 limits -40c typical 125c 0 1 2 3 4 5 0 102030405060708090100 v ol (v) i ol (ma) graph represents 3 limits
? 2011-2012 microchip technology inc. ds41441c-page 367 pic12(l)f1840 figure 31-43: v oh vs. i oh over temperature, v dd = 3.0v figure 31-44: v ol vs. i ol , over temperature, v dd = 3.0v -40c typical 125c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 -15-13-11-9-7-5-3-1 v oh (v) i oh (ma) graph represents 3 limits -40c typical 125c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 5 10 15 20 25 30 35 40 v ol (v) i ol (ma) graph represents 3 limits
pic12(l)f1840 ds41441c-page 368 ? 2011-2012 microchip technology inc. figure 31-45: v oh vs. i oh over temperature, v dd = 1.8v, pic12lf1840 only figure 31-46: v ol vs. i ol over temperature, v dd = 1.8v, pic12lf1840 only -40c typical 125c 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 v oh (v) i oh (ma) graph represents 3 limits -40c typical 125c 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 012345678910 v ol (v) i ol (ma) graph represents 3 limits
? 2011-2012 microchip technology inc. ds41441c-page 369 pic12(l)f1840 figure 31-47: por release voltage figure 31-48: por rearm voltage, pic12f1840 only typical max. min. 1.50 1.52 1.54 1.56 1.58 1.60 1.62 1.64 1.66 1.68 1.70 -60 -40 -20 0 20 40 60 80 100 120 140 voltage (v) temperature (c) max: typical + 3 typical: 25c min: typical - 3 typical max. min. 1.34 1.36 1.38 1.40 1.42 1.44 1.46 1.48 1.50 1.52 1.54 -60 -40 -20 0 20 40 60 80 100 120 140 voltage (v) temperature (c) max: typical + 3 typical: 25c min: typical - 3
pic12(l)f1840 ds41441c-page 370 ? 2011-2012 microchip technology inc. figure 31-49: brown-out reset voltage, borv = 1 , pic12lf1840 only figure 31-50: brown-out reset hysteresis, borv = 1 , pic12lf1840 only typical max. min. 1.80 1.85 1.90 1.95 2.00 -60 -40 -20 0 20 40 60 80 100 120 140 voltage (v) temperature (c) max: typical + 3 min: typical - 3 typical max. min. 0 10 20 30 40 50 60 -60 -40 -20 0 20 40 60 80 100 120 140 voltage (mv) temperature (c) max: typical + 3 typical: 25c min: typical - 3
? 2011-2012 microchip technology inc. ds41441c-page 371 pic12(l)f1840 figure 31-51: brown-out reset voltage, borv = 1 , pic12f1840 only figure 31-52: brown-out reset hysteresis, borv = 1 , pic12f1840 only typical max. min. 2.30 2.35 2.40 2.45 2.50 2.55 2.60 -60 -40 -20 0 20 40 60 80 100 120 140 voltage (v) temperature (c) max: typical + 3 min: typical - 3 typical max. min. 0 10 20 30 40 50 60 70 -60 -40 -20 0 20 40 60 80 100 120 140 voltage (mv) temperature (c) max: typical + 3 typical: 25c min: typical - 3
pic12(l)f1840 ds41441c-page 372 ? 2011-2012 microchip technology inc. figure 31-53: brown-out reset voltage, borv = 0 figure 31-54: brown-out reset hysteresis, borv = 0 typical max. min. 2.55 2.60 2.65 2.70 2.75 2.80 -60 -40 -20 0 20 40 60 80 100 120 140 voltage (v) temperature (c) max: typical + 3 min: typical - 3 typical max. min. 0 10 20 30 40 50 60 70 80 90 -60 -40 -20 0 20 40 60 80 100 120 140 voltage (mv) temperature (c) max: typical + 3 typical: 25c min: typical - 3
? 2011-2012 microchip technology inc. ds41441c-page 373 pic12(l)f1840 figure 31-55: low power brown-out reset voltage, lpbor = 0 figure 31-56: low power brown-out reset hysteresis, lpbor = 0 typical max. min. 1.80 1.90 2.00 2.10 2.20 2.30 2.40 2.50 -60 -40 -20 0 20 40 60 80 100 120 140 voltage (v) temperature (c) max: typical + 3 min: typical - 3 typical max. min. 0 5 10 15 20 25 30 35 40 45 -60 -40 -20 0 20 40 60 80 100 120 140 voltage (mv) temperature (c) max: typical + 3 typical: 25c min: typical - 3
pic12(l)f1840 ds41441c-page 374 ? 2011-2012 microchip technology inc. figure 31-57: wdt time-out period figure 31-58: pwrt period typical max. min. 10 12 14 16 18 20 22 24 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 time (ms) v dd (v) max: typical + 3 (-40c to +125c) typical: statistical mean @ 25c min: typical - 3 (-40c to +125c) typical max. min. 40 50 60 70 80 90 100 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 time (ms) v dd (v) max: typical + 3 (-40c to +125c) typical: statistical mean @ 25c min: typical - 3 (-40c to +125c)
? 2011-2012 microchip technology inc. ds41441c-page 375 pic12(l)f1840 figure 31-59: fvr stabilization period typical max. 0 5 10 15 20 25 30 35 40 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 time (us) v dd (v) max: typical + 3 typical: statistical mean @ 25c note: the fvr stabilization period applies when: 1) coming out of reset or exiting sleep mode for pic12/16lfxxxx devices. 2) when exiting sleep mode with vregpm = 1 for pic12/16fxxxx devices in all other cases, the fvr is stable when released from reset.
pic12(l)f1840 ds41441c-page 376 ? 2011-2012 microchip technology inc. figure 31-60: comparator hysteres is, normal-power mode, cxsp = 1 , cxhys = 1 figure 31-61: comparator hyster esis, low-power mode, cxsp = 0 , cxhys = 1 min. typical max. 0 10 20 30 40 50 60 70 80 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 hysteresis (mv) v dd (v) max: typical + 3 typical: 25c min: typical - 3 min. typical max. 0 2 4 6 8 10 12 14 16 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 hysteresis (mv) v dd (v) max: typical + 3 typical: 25c min: typical - 3
? 2011-2012 microchip technology inc. ds41441c-page 377 pic12(l)f1840 figure 31-62: comparator response ti me, normal-power mode, cxsp = 1 figure 31-63: comparator response time over temperature, normal-power mode, cxsp = 1 max. typical 0 50 100 150 200 250 300 350 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 time (ns) v dd (v) max: typical + 3 typical: 25c -40c typical 125c 0 50 100 150 200 250 300 350 400 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 time (ns) v dd (v) graph represents 3 limits
pic12(l)f1840 ds41441c-page 378 ? 2011-2012 microchip technology inc. figure 31-64: comparator input offset at 25c, normal-power mode, cxsp = 1 , pic12f1840 only max. typical min. -50 -40 -30 -20 -10 0 10 20 30 40 50 0.0 1.0 2.0 3.0 4.0 5.0 offset voltage (mv) common mode voltage (v) max: typical + 3 typical: 25c min: typical - 3
? 2011-2012 microchip technology inc. ds41441c-page 379 pic12(l)f1840 figure 31-65: lfintosc frequency over v dd and temperature, pic12lf1840 only figure 31-66: lfintosc frequency over v dd and temperature, pic12f1840 only typical max. min. 20 22 24 26 28 30 32 34 36 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 frequency (khz) v dd (v) max: typical + 3 (-40c to +125c) typical: statistical mean @ 25c min: typical - 3 (-40c to +125c) typical max. min. 20 22 24 26 28 30 32 34 36 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 frequency (khz) v dd (v) max: typical + 3 (-40c to +125c) typical: statistical mean @ 25c min: typical - 3 (-40c to +125c)
pic12(l)f1840 ds41441c-page 380 ? 2011-2012 microchip technology inc. figure 31-67: cap sense current sink/source characteristics , fixed voltage reference (cpsrm = 0 ), high current range (cpsrng = 11 ) figure 31-68: cap sense current sink/source characteristics , fixed voltage reference (cpsrm = 0 ), medium current range (cpsrng = 10 ) sink typical sink max. sink min. source typical source min. source max. -20 -15 -10 -5 0 5 10 15 20 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pin (ua) v dd (v) max: typical + 3 typical: min: typical - 3 sink typical sink max. sink min. source typical source min. source max. -5 -4 -3 -2 -1 0 1 2 3 4 5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pin (ua) v dd (v) max: typical + 3 typical: min: typical - 3
? 2011-2012 microchip technology inc. ds41441c-page 381 pic12(l)f1840 figure 31-69: cap sense current sink/source characteristics , fixed voltage reference (cpsrm = 0 ), low current range (cpsrng = 01 ) sink typical sink max. sink min. source typical source min. source max. -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pin (ua) v dd (v) max: typical + 3 typical: min: typical - 3
pic12(l)f1840 ds41441c-page 382 ? 2011-2012 microchip technology inc. notes:
? 2011-2012 microchip technology inc. ds41441c-page 383 pic12(l)f1840 32.0 development support the pic ? microcontrollers and dspic ? digital signal controllers are supported with a full range of software and hardware development tools: ? integrated development environment - mplab ? ide software ? compilers/assemblers/linkers - mplab c compiler for various device families - hi-tech c for various device families - mpasm tm assembler -mplink tm object linker/ mplib tm object librarian - mplab assembler/linker/librarian for various device families ? simulators - mplab sim software simulator ?emulators - mplab real ice? in-circuit emulator ? in-circuit debuggers - mplab icd 3 - pickit? 3 debug express ? device programmers - pickit? 2 programmer - mplab pm3 device programmer ? low-cost demonstration/development boards, evaluation kits, and starter kits 32.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. the mplab ide is a windows ? operating system-based application that contains: ? a single graphical interface to all debugging tools - simulator - programmer (sold separately) - in-circuit emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor with color-coded context ? a multiple project manager ? customizable data windows with direct edit of contents ? high-level source code debugging ? mouse over variable inspection ? drag and drop variables from source to watch windows ? extensive on-line help ? integration of select third party tools, such as iar c compilers the mplab ide allows you to: ? edit your source files (either c or assembly) ? one-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) ? debug using: - source files (c or assembly) - mixed c and assembly - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increased flexibility and power.
pic12(l)f1840 ds41441c-page 384 ? 2011-2012 microchip technology inc. 32.2 mplab c compilers for various device families the mplab c compiler code development systems are complete ansi c compilers for microchip?s pic18, pic24 and pic32 families of microcontrollers and the dspic30 and dspic33 families of digital signal control- lers. these compilers provide powerful integration capabilities, superior code optimization and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 32.3 hi-tech c for various device families the hi-tech c compiler code development systems are complete ansi c compilers for microchip?s pic family of microcontrollers and the dspic family of digital signal controllers. these compilers provide powerful integration capabilities, omniscient code generation and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. the compilers include a macro assembler, linker, pre- processor, and one-step driver, and can run on multiple platforms. 32.4 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for pic10/12/16/18 mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: ? integration into mplab ide projects ? user-defined macros to streamline assembly code ? conditional assembly for multi-purpose source files ? directives that allow complete control over the assembly process 32.5 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c18 c compiler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: ? efficient linking of single libraries instead of many smaller files ? enhanced code maintainability by grouping related modules together ? flexible creation of libraries with easy module listing, replacement, deletion and extraction 32.6 mplab assembler, linker and librarian for various device families mplab assembler produces relocatable machine code from symbolic assembly language for pic24, pic32 and dspic devices. mplab c compiler uses the assembler to produce its object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: ? support for the entire device instruction set ? support for fixed-point and floating-point data ? command line interface ? rich directive set ? flexible macro language ? mplab ide compatibility
? 2011-2012 microchip technology inc. ds41441c-page 385 pic12(l)f1840 32.7 mplab sim software simulator the mplab sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic ? dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab sim software simulator fully supports symbolic debugging using the mplab c compilers, and the mpasm and mplab assemblers. the soft- ware simulator offers the flexibility to develop and debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software development tool. 32.8 mplab real ice in-circuit emulator system mplab real ice in-circuit emulator system is microchip?s next generation high-speed emulator for microchip flash dsc and mcu devices. it debugs and programs pic ? flash mcus and dspic ? flash dscs with the easy-to-use, powerful graphical user interface of the mplab integrated development environment (ide), included with each kit. the emulator is connected to the design engineer?s pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with in- circuit debugger systems (rj11) or with the new high- speed, noise tolerant, low-voltage differential signal (lvds) interconnection (cat5). the emulator is field upgradable through future firmware downloads in mplab ide. in upcoming releases of mplab ide, new devices will be supported, and new features will be added. mplab real ice offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 32.9 mplab icd 3 in-circuit debugger system mplab icd 3 in-circuit debugger system is micro- chip's most cost effective high-speed hardware debugger/programmer for microchip flash digital sig- nal controller (dsc) and microcontroller (mcu) devices. it debugs and programs pic ? flash microcon- trollers and dspic ? dscs with the powerful, yet easy- to-use graphical user interface of mplab integrated development environment (ide). the mplab icd 3 in-circuit debugger probe is con- nected to the design engineer's pc using a high-speed usb 2.0 interface and is connected to the target with a connector compatible with the mplab icd 2 or mplab real ice systems (rj-11). mplab icd 3 supports all mplab icd 2 headers. 32.10 pickit 3 in-circuit debugger/ programmer and pickit 3 debug express the mplab pickit 3 allows debugging and program- ming of pic ? and dspic ? flash microcontrollers at a most affordable price point using the powerful graphical user interface of the mplab integrated development environment (ide). the mplab pickit 3 is connected to the design engineer's pc using a full speed usb interface and can be connected to the target via an microchip debug (rj-11) connector (compatible with mplab icd 3 and mplab real ice). the connector uses two device i/o pins and the reset line to imple- ment in-circuit debugging and in-circuit serial pro- gramming?. the pickit 3 debug express include the pickit 3, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software.
pic12(l)f1840 ds41441c-page 386 ? 2011-2012 microchip technology inc. 32.11 pickit 2 development programmer/debugger and pickit 2 debug express the pickit? 2 development programmer/debugger is a low-cost development tool with an easy to use inter- face for programming and debugging microchip?s flash families of microcontrollers. the full featured windows ? programming interface supports baseline (pic10f, pic12f5xx, pic16f5xx), midrange (pic12f6xx, pic16f), pic18f, pic24, dspic30, dspic33, and pic32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many microchip serial eeprom products. with microchip?s powerful mplab integrated development environment (ide) the pickit? 2 enables in-circuit debugging on most pic ? microcon- trollers. in-circuit-debugging runs, halts and single steps the program while the pic microcontroller is embedded in the application. when halted at a break- point, the file registers can be examined and modified. the pickit 2 debug express include the pickit 2, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software. 32.12 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modu- lar, detachable socket assembly to support various package types. the icsp? cable assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc connection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an mmc card for file storage and data applications. 32.13 demonstration/development boards, evaluation kits, and starter kits a wide variety of demonstration, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully func- tional systems. most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, switches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demon- stration/development board series of circuits, microchip has a line of evaluation kits and demonstration software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. also available are starter kits that contain everything needed to experience the specified device. this usually includes a single application and debug capability, all on one board. check the microchip web page ( www.microchip.com ) for the complete list of demonstration, development and evaluation kits.
? 2011-2012 microchip technology inc. ds41441c-page 387 pic12(l)f1840 33.0 packaging information 33.1 package marking information * standard picmicro ? device marking consists of microchip part number, year code, week code and traceability code. for picmicro device marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price. legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 8-lead pdip (300 mil) example xxxxxxxx xxxxxnnn yyww 12f1840 /p017 1212 8-lead soic (3.90 mm) example nnn 017 12f1840 /sn1212
pic12(l)f1840 ds41441c-page 388 ? 2011-2012 microchip technology inc. 33.2 package marking information 8-lead dfn (3x3x0.9 mm) example xxxx nnn yyww pin 1 pin 1 mfq0 1212 017 table 33-1: 8-lead 3x3 dfn (mf) top marking part number marking pic12f1840-e/mf mfq0 pic12f1840(t)-i/mf mfr0 pic12lf1840-e/mf mfs0 pic12lf1840(t)-i/mf mft0
? 2011-2012 microchip technology inc. ds41441c-page 389 pic12(l)f1840 33.3 package details the following sections give the technical details of the packages. n e1 note 1 d 12 3 a a1 a2 l b1 b e e eb c
pic12(l)f1840 ds41441c-page 390 ? 2011-2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2011-2012 microchip technology inc. ds41441c-page 391 pic12(l)f1840 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic12(l)f1840 ds41441c-page 392 ? 2011-2012 microchip technology inc.
? 2011-2012 microchip technology inc. ds41441c-page 393 pic12(l)f1840 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic12(l)f1840 ds41441c-page 394 ? 2011-2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2011-2012 microchip technology inc. ds41441c-page 395 pic12(l)f1840 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic12(l)f1840 ds41441c-page 396 ? 2011-2012 microchip technology inc. notes:
? 2011-2012 microchip technology inc. preliminary ds41441c-page 397 pic12(l)f1840 appendix a: data sheet revision history revision a (02/2011) original release of this data sheet. revision b (05/2011) updated ?special microcontroller features? and ?low-power features? sections; updated section 30.3, ?dc characteristics: pic12(l)f1840-i/e (power-down)?; updated the packaging information section. revision c (12/2012) updated electrical specifications and added character- ization data. appendix b: migrating from other pic ? devices this section provides comparisons when migrating from other similar pic ? devices to the pic12(l)f1840 family of devices. b.1 pic12f683 to pic12(l)f1840 table b-1: feature comparison feature pic12f683 pic12(l)f1840 max. operating speed 20 mhz 32 mhz max. program memory (words) 2k 4k max. sram (bytes) 128 256 max. eeprom (bytes) 256 256 adc resolution 10-bit 10-bit timers (8/16-bit) 2/1 2/1 brown-out reset y y internal pull-ups gp<5:4>, gp<2:0> ra<5:0> interrupt-on-change gp<5:0> ra<5:0>, edge selectable comparator 1 1 eusart n y extended wdt n y software control option of wdt/bor yy intosc frequencies 31 khz - 8 mhz 31 khz - 32 mhz clock switching y y capacitive sensing n y ccp/eccp 1/0 0/1 enhanced pic16 cpu ny msspx/sspx n y reference clock n y data signal modulator ny sr latch n y voltage reference n y dac n y
pic12(l)f1840 ds41441c-page 398 preliminary ? 2011-2012 microchip technology inc. notes:
? 2011-2012 microchip technology inc. ds41441c-page 399 pic12(l)f1840 index a absolute maximum ratings .............................................. 313 ac characteristics industrial and extended ............................................ 328 load conditions ........................................................ 327 ackstat ......................................................................... 237 ackstat status flag ...................................................... 237 adc .................................................................................. 119 acquisition requirements ......................................... 129 associated registers.................................................. 131 block diagram........................................................... 119 calculating acquisition time..................................... 129 channel selection..................................................... 120 configuration............................................................. 120 configuring interrupt ................................................. 124 conversion clock...................................................... 120 conversion procedure .............................................. 124 internal sampling switch (r ss ) impedance.............. 129 interrupts................................................................... 122 operation .................................................................. 123 operation during sleep ............................................ 123 port configuration ..................................................... 120 reference voltage (v ref )......................................... 120 source impedance.................................................... 129 special event trigger................................................ 123 specifications.................................................... 334, 335 starting an adc conversion..................................... 122 adcon0 register....................................................... 22, 125 adcon1 register....................................................... 22, 126 addfsr ........................................................................... 303 addwfc .......................................................................... 303 adresh register............................................................... 22 adresh register (adfm = 0) ......................................... 127 adresh register (adfm = 1) ......................................... 128 adresl register (adfm = 0).......................................... 127 adresl register (adfm = 1).......................................... 128 alternate pin function....................................................... 101 analog-to-digital converter. see adc ansela register ............................................................. 106 apfcon0 register........................................................... 102 assembler mpasm assembler................................................... 384 b baudcon register.......................................................... 269 bf ............................................................................. 237, 239 bf status flag .......................................................... 237, 239 block diagram capacitive sensing ........................................... 287, 288 block diagrams (ccp) capture mode operation ............................... 180 adc .......................................................................... 119 adc transfer function ............................................. 130 analog input model ........................................... 130, 146 ccp pwm................................................................. 184 clock source............................................................... 40 comparator ............................................................... 142 compare ................................................................... 182 crystal operation .................................................. 42, 43 digital-to-analog converter (dac)............................ 134 eusart receive ..................................................... 258 eusart transmit .................................................... 257 external rc mode....................................................... 44 fail-safe clock monitor (fscm)................................. 52 generic i/o port........................................................ 101 interrupt logic............................................................. 69 on-chip reset circuit................................................. 61 pic12(l)f1840 ....................................................... 8, 11 pwm (enhanced) ..................................................... 188 resonator operation .................................................. 42 timer0 ...................................................................... 149 timer1 ...................................................................... 153 timer1 gate.............................................. 158, 159, 160 timer2 ...................................................................... 165 voltage reference.................................................... 113 voltage reference output buffer example .............. 134 borcon register.............................................................. 63 bra .................................................................................. 304 break character (12-bit) transmit and receive ............... 278 brown-out reset (bor)...................................................... 63 specifications ........................................................... 332 timing and characteristics ....................................... 331 c c compilers mplab c18.............................................................. 384 call................................................................................. 305 callw ............................................................................. 305 capacitive sensing ........................................................... 287 associated registers w/ capacitive sensing............. 294 specifications ........................................................... 344 capture module. see enhanced capture/compare/ pwm (eccp) capture/compare/pwm ................................................... 179 capture/compare/pwm (ccp) associated registers w/ capture ............................. 181 associated registers w/ compare ........................... 183 associated registers w/ pwm ......................... 187, 196 capture mode........................................................... 180 ccpx pin configuration............................................ 180 compare mode......................................................... 182 ccpx pin configuration.................................... 182 software interrupt mode ........................... 180, 182 special event trigger ....................................... 182 timer1 mode resource ............................ 180, 182 prescaler .................................................................. 180 pwm mode duty cycle ........................................................ 185 effects of reset ................................................ 187 example pwm frequencies and resolutions, 20 mhz................................ 186 example pwm frequencies and resolutions, 32 mhz................................ 186 example pwm frequencies and resolutions, 8 mhz .................................. 186 operation in sleep mode.................................. 187 resolution ........................................................ 186 system clock frequency changes .................. 187 pwm operation ........................................................ 184 pwm overview......................................................... 184 pwm period ............................................................. 185 pwm setup .............................................................. 185 ccp1as register ............................................................. 198 ccp1con register............................................................ 24 ccpr1h register............................................................... 24 ccpr1l register ............................................................... 24 ccpxcon (eccpx) register........................................... 197
pic12(l)f1840 ds41441c-page 400 ? 2011-2012 microchip technology inc. clkrcon register ............................................................ 58 clock accuracy with asynchronous operation ................. 266 clock sources external modes ........................................................... 41 ec ....................................................................... 41 hs ....................................................................... 41 lp........................................................................ 41 ost..................................................................... 42 rc....................................................................... 43 xt ....................................................................... 41 internal modes ............................................................ 44 hfintosc.......................................................... 45 internal oscillator clock switch timing............... 47 lfintosc .......................................................... 45 mfintosc ......................................................... 45 clock switching................................................................... 49 cm1con0 register .......................................................... 147 cm1con1 register .......................................................... 148 cmout register............................................................... 148 code examples adc conversion ....................................................... 124 changing between capture prescalers .................... 180 initializing porta..................................................... 103 write verify ................................................................. 96 writing to flash program memory .............................. 94 comparator associated registers ................................................ 148 operation .................................................................. 141 comparator module .......................................................... 141 c1 output state versus input conditions ................. 143 comparator specifications ................................................ 337 comparators c2out as t1 gate ................................................... 155 compare module. see enhanced capture/compare/ pwm (eccp) config1 register.............................................................. 34 config2 register.............................................................. 36 core function register ....................................................... 21 cpscon0 register .......................................................... 293 cpscon1 register .......................................................... 294 customer change notification service ............................. 405 customer notification service........................................... 405 customer support ............................................................. 405 d daccon0 (digital-to-analog converter control 0) register..................................................................... 136 daccon1 (digital-to-analog converter control 1) register..................................................................... 136 data eeprom memory ...................................................... 87 associated registers .................................................. 99 code protection .......................................................... 88 reading....................................................................... 88 writing......................................................................... 88 data memory....................................................................... 15 dc and ac characteristics ............................................... 345 dc characteristics extended and industrial ............................................ 323 industrial and extended ............................................ 316 development support ....................................................... 383 device configuration........................................................... 33 code protection .......................................................... 37 configuration word ..................................................... 33 user id .................................................................. 37, 38 device id register .............................................................. 38 device overview ............................................................. 7, 83 digital-to-analog converter (dac) ................................... 133 effects of a reset ..................................................... 134 specifications ........................................................... 337 e eccp/ccp. see enhanced capture/compare/pwm eeadr registers ............................................................... 87 eeadrh registers............................................................. 87 eeadrl register ............................................................... 97 eeadrl registers ............................................................. 87 eecon1 register......................................................... 87, 98 eecon2 register......................................................... 87, 99 eedath register............................................................... 97 eedatl register ............................................................... 97 eeprom data memory avoiding spurious write ............................................. 88 write verify ................................................................. 96 effects of reset pwm mode............................................................... 187 electrical specifications .................................................... 313 enhanced capture/compare/pwm (eccp)..................... 180 enhanced pwm mode.............................................. 188 auto-restart ..................................................... 192 auto-shutdown.................................................. 191 full-bridge mode .............................................. 191 half-bridge application ..................................... 190 half-bridge application examples .................... 193 half-bridge mode.............................................. 190 output relationships (active-high and active-low)............................................... 189 output relationships diagram.......................... 189 programmable dead band delay..................... 193 shoot-through current...................................... 193 start-up considerations.................................... 194 specifications ........................................................... 334 enhanced mid-range cpu.................................................. 11 enhanced universal synchronous asynchronous receiver transmitter (eusart) .............................. 257 errata .................................................................................... 5 eusart ........................................................................... 257 associated registers baud rate generator ....................................... 271 asynchronous mode ................................................. 259 12-bit break transmit and receive .................. 278 associated registers receive .................................................... 265 transmit.................................................... 261 auto-wake-up on break ................................... 276 baud rate generator (brg) ............................ 270 clock accuracy................................................. 266 receiver ........................................................... 262 setting up 9-bit mode with address detect ...... 264 transmitter ....................................................... 259 baud rate generator (brg) auto baud rate detect..................................... 275 baud rate error, calculating............................ 270 baud rates, asynchronous modes .................. 272 formulas........................................................... 271 high baud rate select (brgh bit) .................. 270 synchronous master mode............................... 279, 283 associated registers receive .................................................... 282 transmit.................................................... 280 reception ......................................................... 281 transmission .................................................... 279 synchronous slave mode
? 2011-2012 microchip technology inc. ds41441c-page 401 pic12(l)f1840 associated registers receive..................................................... 284 transmit.................................................... 283 reception.......................................................... 284 transmission .................................................... 283 extended instruction set addfsr ................................................................... 303 f fail-safe clock monitor....................................................... 52 fail-safe condition clearing ....................................... 52 fail-safe detection ..................................................... 52 fail-safe operation..................................................... 52 reset or wake-up from sleep..................................... 52 firmware instructions........................................................ 299 fixed voltage reference (fvr) ........................................ 113 associated registers ................................................ 115 flash program memory ...................................................... 87 erasing........................................................................ 92 modifying..................................................................... 95 writing......................................................................... 92 fsr0h register.................................................................. 21 fsr0l register .................................................................. 21 fsr1h register.................................................................. 21 fsr1l register .................................................................. 21 fvrcon (fixed voltage reference control) register ..... 115 i i 2 c mode (mssp) slave mode transmission .................................................... 223 i 2 c mode (msspx) acknowledge sequence timing................................ 241 bus collision during a repeated start condition ................... 246 during a stop condition.................................... 248 effects of a reset...................................................... 242 i 2 c clock rate w/brg.............................................. 250 master mode operation .......................................................... 233 reception.......................................................... 239 start condition timing .............................. 235, 236 transmission .................................................... 237 multi-master communication, bus collision and arbitration ......................................................... 242 multi-master mode .................................................... 242 read/write bit information (r/w bit) ........................ 218 sleep operation ........................................................ 242 stop condition timing............................................... 241 indf0 register ................................................................... 21 indf1 register ................................................................... 21 indirect addressing ............................................................. 29 instruction format ............................................................. 300 instruction set ................................................................... 299 addlw ..................................................................... 303 addwf..................................................................... 303 addwfc .................................................................. 303 andlw ..................................................................... 303 andwf..................................................................... 303 bra........................................................................... 304 call ......................................................................... 305 callw...................................................................... 305 lslf ......................................................................... 307 lsrf......................................................................... 307 movf........................................................................ 307 moviw ..................................................................... 308 movlb ..................................................................... 308 movwi ..................................................................... 309 option.................................................................... 309 reset...................................................................... 309 subwfb .................................................................. 311 tris ......................................................................... 312 bcf .......................................................................... 304 bsf........................................................................... 304 btfsc...................................................................... 304 btfss ...................................................................... 304 call......................................................................... 305 clrf ........................................................................ 305 clrw ....................................................................... 305 clrwdt .................................................................. 305 comf ....................................................................... 305 decf........................................................................ 305 decfsz ................................................................... 306 goto ....................................................................... 306 incf ......................................................................... 306 incfsz..................................................................... 306 iorlw...................................................................... 306 iorwf...................................................................... 306 movlw .................................................................... 308 movwf.................................................................... 308 nop.......................................................................... 309 retfie..................................................................... 310 retlw ..................................................................... 310 return................................................................... 310 rlf........................................................................... 310 rrf .......................................................................... 311 sleep ...................................................................... 311 sublw..................................................................... 311 subwf..................................................................... 311 swapf..................................................................... 312 xorlw .................................................................... 312 xorwf .................................................................... 312 intcon register................................................................ 74 internal oscillator block intosc specifications ................................................... 329 internal sampling switch (r ss ) impedance ..................... 129 internet address ............................................................... 405 interrupt-on-change......................................................... 109 associated registers................................................ 112 interrupts ............................................................................ 69 adc .......................................................................... 124 associated registers w/ interrupts .............................. 78 configuration word w/ clock sources........................ 56 configuration word w/ reference clock sources ...... 59 tmr1........................................................................ 157 intosc specifications ..................................................... 329 iocaf register ................................................................ 111 iocan register ................................................................ 111 iocap register ................................................................ 111 l lata register .................................................................. 106 load conditions................................................................ 327 lslf ................................................................................. 307 lsrf ................................................................................ 307 m master synchronous serial port. see msspx mclr ................................................................................. 64 internal........................................................................ 64 mdcarh register............................................................ 176
pic12(l)f1840 ds41441c-page 402 ? 2011-2012 microchip technology inc. mdcarl register............................................................. 177 mdcon register .............................................................. 174 mdsrc register............................................................... 175 memory organization.......................................................... 13 data ............................................................................ 15 program ...................................................................... 13 microchip internet web site .............................................. 405 migrating from other pic microcontroller devices............. 397 moviw.............................................................................. 308 movlb.............................................................................. 308 movwi.............................................................................. 309 mplab asm30 assembler, linker, librarian ................... 384 mplab integrated development environment software .. 383 mplab pm3 device programmer..................................... 386 mplab real ice in-circuit emulator system................. 385 mplink object linker/mplib object librarian ................ 384 msspx .............................................................................. 201 i 2 c mode operation .................................................. 215 spi mode .................................................................. 204 sspxbuf register ................................................... 208 sspxsr register...................................................... 208 o opcode field descriptions ............................................. 299 option ............................................................................ 309 option_reg register .................................................... 151 osccon register .............................................................. 54 oscillator associated registers .................................................. 56 oscillator module .......................... ...................................... 39 ech ............................................................................ 39 ecl ............................................................................. 39 ecm ............................................................................ 39 hs ............................................................................... 39 intosc ...................................................................... 39 lp................................................................................ 39 rc............................................................................... 39 xt ............................................................................... 39 oscillator parameters.................. ..................... .......... ....... 329 oscillator specifications .................................................... 328 oscillator start-up timer (ost) specifications............................................................ 332 oscillator switching fail-safe clock monitor............................................... 52 two-speed clock start-up .......................................... 50 oscstat register............................................................. 55 osctune register ............................................................ 56 p p1a/p1b/p1c/p1d. see enhanced capture/compare/ pwm (eccp) ............................................................ 188 packaging ......................................................................... 387 marking ............................................................. 387, 388 pdip details.............................................................. 389 pcl and pclath ............................................................... 11 pcl register....................................................................... 21 pclath register................................................................ 21 pcon register ............................................................. 22, 67 pie1 register ................................................................ 22, 75 pie2 register ...................................................................... 76 pinout descriptions pic12(l)f1840 ............................................................. 9 pir1 register................................................................ 22, 77 pir2 register................................................................ 22, 78 porta.............................................................................. 103 ansela register ..................................................... 103 associated registers ................................................ 107 configuration word w/ porta................................. 107 lata register ............................................................ 23 porta register ......................................................... 22 specifications ........................................................... 330 porta register ............................................................... 105 power-down mode (sleep)................................................. 79 associated registers .......................................... 82, 177 power-on reset .................................................................. 62 power-up time-out sequence ............................................ 64 power-up timer (pwrt) .................................................... 62 specifications ........................................................... 332 pr2 register ...................................................................... 22 precision internal oscillator parameters .......................... 329 program memory ................................................................ 13 map and stack (banks 16-23) .................................... 19 map and stack (banks 24-30) .................................... 19 map and stack (banks 8-14) ...................................... 19 map and stack (pic12(l)f1840)................................ 14 map and stack (pic12f/lf1840) ......................... 13, 14 programming, device instructions.................................... 299 pstrxcon register ........................................................ 199 pwm (eccp module) pwm steering........................................................... 194 steering synchronization.......................................... 194 pwm mode. see enhanced capture/compare/pwm ...... 188 pwm steering................................................................... 194 pwm1con register......................................................... 199 r rcreg............................................................................. 264 rcreg register ................................................................ 23 rcsta register ......................................................... 23, 268 reader response............................................................. 406 read-modify-write operations ......................................... 299 reference clock ................................................................. 57 associated registers .................................................. 59 registers adcon0 (adc control 0) ........................................ 125 adcon1 (adc control 1) ........................................ 126 adresh (adc result high) with adfm = 0) .......... 127 adresh (adc result high) with adfm = 1) .......... 128 adresl (adc result low) with adfm = 0)............ 127 adresl (adc result low) with adfm = 1)............ 128 ansela (porta analog select)............................. 106 apfcon0 (alternate pin function control 0) .......... 102 baudcon (baud rate control)............................... 269 borcon brown-out reset control) .......................... 63 ccp1as (ccp1 auto-shutdown control) ................ 198 ccpxcon (eccpx control)..................................... 197 clkrcon (reference clock control)........................ 58 cm1con0 (c1 control)............................................ 147 cm1con1 (c1 control 1)......................................... 148 cmout (comparator output) .................................. 148 configuration word 1.................................................. 34 configuration word 2.................................................. 36 core function, summary............................................ 21 cpscon0 (capacitive sensing control register 0) 293 cpscon1 (capacitive sensing control register 1) 294 daccon0 ................................................................ 136 daccon1 ................................................................ 136 device id .................................................................... 38 eeadrl (eeprom address) .................................... 97 eecon1 (eeprom control 1) .................................. 98 eecon2 (eeprom control 2) .................................. 99 eedath (eeprom data).......................................... 97
? 2011-2012 microchip technology inc. ds41441c-page 403 pic12(l)f1840 eedatl (eeprom data) .......................................... 97 fvrcon................................................................... 115 intcon (interrupt control)......................................... 74 iocaf (interrupt-on-change porta flag).............. 111 iocan (interrupt-on-change porta negative edge) ................................................. 111 iocap (interrupt-on-change porta positive edge)................................................... 111 lata (data latch porta)....................................... 106 mdcarh (modulation high carrier control register) ........................................................... 176 mdcarl (modulation low carrier control register) 177 mdcon (modulation control register) .................... 174 mdsrc (modulation source control register) ........ 175 option_reg (option) ......................................... 151 osccon (oscillator control) ........ ............................. 54 oscstat (oscillator status) ..................................... 55 osctune (oscillator tuning) .................................... 56 pcon (power control register) ................................. 67 pcon (power control) ............................................... 67 pie1 (peripheral interrupt enable 1)........................... 75 pie2 (peripheral interrupt enable 2)........................... 76 pir1 (peripheral interrupt register 1) ........................ 77 pir2 (peripheral interrupt request 2) ........................ 78 porta...................................................................... 105 pstrxcon (pwm steering control) ....................... 199 pwm1con (enhanced pwm control) ..................... 199 rcreg ..................................................................... 275 rcsta (receive status and control)....................... 268 spbrgh................................................................... 270 spbrgl ................................................................... 270 special function, summary ........................................ 22 srcon0 (sr latch control 0) ................................. 139 srcon1 (sr latch control 1) ................................. 140 sspstat (ssp status)............................................ 251 sspxadd (msspx address and baud rate, i 2 c mode) ......................................................... 255 sspxcon1 (msspx control 1) ................................ 252 sspxcon2 (sspx control 2) ................................... 253 sspxcon3 (sspx control 3) ................................... 254 sspxmsk (sspx mask) ........................................... 255 status...................................................................... 16 t1con (timer1 control)........................................... 161 t1gcon (timer1 gate control) ............................... 162 t2con...................................................................... 167 trisa (tri-state porta)......................................... 105 txsta (transmit status and control) ...................... 267 vregcon (voltage regulator control) ..................... 82 wdtcon (watchdog timer control) ......................... 85 wpub (weak pull-up portb) ................................. 107 reset .............................................................................. 309 reset................................................................................... 61 reset instruction ................................................................. 64 resets................................................................................. 61 associated registers .................................................. 68 revision history ................................................................ 397 s shoot-through current ...................................................... 193 software simulator (mplab sim)..................................... 385 spbrg register ................................................................. 23 spbrgh register ............................................................ 270 spbrgl register ............................................................. 270 special event trigger........................................................ 123 special function registers (sfrs)..................................... 22 spi mode (msspx) associated registers................................................ 212 spi clock.................................................................. 208 sr latch........................................................................... 137 associated registers w/ sr latch............................. 140 srcon0 register ............................................................ 139 srcon1 register ............................................................ 140 ssp1add register............................................................. 24 ssp1buf register ............................................................. 24 ssp1con register ............................................................ 24 ssp1con2 register .......................................................... 24 ssp1con3 register .......................................................... 24 ssp1msk register ............................................................ 24 ssp1stat register ........................................................... 24 sspstat register ........................................................... 251 sspxadd register........................................................... 255 sspxcon1 register ........................................................ 252 sspxcon2 register ........................................................ 253 sspxcon3 register ........................................................ 254 sspxmsk register........................................................... 255 sspxov ........................................................................... 239 sspxov status flag ........................................................ 239 sspxstat register r/w bit ..................................................................... 218 stack................................................................................... 27 accessing ................................................................... 27 reset .......................................................................... 29 stack overflow/underflow .................................................. 64 status register ............................................................... 16 subwfb .......................................................................... 311 t t1con register ......................................................... 22, 161 t1gcon register ............................................................ 162 t2con (timer2) register................................................. 167 t2con register ................................................................. 22 temperature indicator associated registers................................................ 118 temperature indicator module.......................................... 117 thermal considerations.................................................... 326 timer0 .............................................................................. 149 associated registers................................................ 151 operation.................................................................. 149 specifications ........................................................... 333 timer1 .............................................................................. 153 associated registers ................................................. 163 asynchronous counter mode ................................... 155 reading and writing ......................................... 155 clock source selection ............................................ 154 interrupt .................................................................... 157 operation.................................................................. 154 operation during sleep ............................................ 157 oscillator.............................. ..................... .......... ...... 155 prescaler .................................................................. 155 specifications ........................................................... 333 timer1 gate selecting source .............................................. 155 tmr1h register....................................................... 153 tmr1l register ....................................................... 153 timer2 .............................................................................. 165 associated registers ................................................. 168 timer2/4/6 associated registers ................................................. 168 timers timer1 t1con ............................................................. 161 t1gcon........................................................... 162
pic12(l)f1840 ds41441c-page 404 ? 2011-2012 microchip technology inc. timer2 t2con.............................................................. 167 timing diagrams acknowledge sequence ........................................... 241 adc conversion ....................................................... 335 adc conversion (sleep mode)................................. 336 asynchronous reception .......................................... 264 asynchronous transmission ..................................... 260 asynchronous transmission (back to back) ............ 260 auto wake-up bit (wue) during normal operation . 277 auto wake-up bit (wue) during sleep .................... 277 automatic baud rate calibration .............................. 275 baud rate generator with clock arbitration ............. 234 brg reset due to sda arbitration during start condition........................................................... 245 brown-out reset (bor) ............................................ 331 brown-out reset situations ........................................ 63 bus collision during a repeated start condition (case 1) ............................................................ 246 bus collision during a repeated start condition (case 2) ............................................................ 247 bus collision during a start condition (scl = 0) ..... 245 bus collision during a stop condition (case 1) ....... 248 bus collision during a stop condition (case 2) ....... 248 bus collision during start condition (sda only) ...... 244 bus collision for transmit and acknowledge............ 243 clkout and i/o....................................................... 330 clock synchronization .............................................. 231 clock timing ............................................................. 328 comparator output ................................................... 141 enhanced capture/compare/pwm (eccp) ............. 334 fail-safe clock monitor (fscm) ................................. 53 first start bit timing ................................................. 235 half-bridge pwm output .................................. 190, 193 i 2 c bus data ............................................................. 343 i 2 c bus start/stop bits.............................................. 342 i 2 c master mode (7 or 10-bit transmission) ............ 238 i 2 c master mode (7-bit reception) ........................... 240 i 2 c stop condition receive or transmit mode ......... 242 int pin interrupt.......................................................... 72 internal oscillator switch timing................................. 48 pwm auto-shutdown ................................................ 192 firmware restart .............................................. 191 pwm output (active-high)........................................ 189 pwm output (active-low) ........................................ 189 repeat start condition.............................................. 236 reset start-up sequence............................................ 65 reset, wdt, ost and power-up timer ................... 331 send break character sequence ............................. 278 spi master mode (cke = 1, smp = 1) ..................... 339 spi mode (master mode) .......................................... 208 spi slave mode (cke = 0) ....................................... 340 spi slave mode (cke = 1) ....................................... 340 synchronous reception (master mode, sren) ....... 282 synchronous transmission....................................... 280 synchronous transmission (through txen) ........... 280 timer0 and timer1 external clock ........................... 333 timer1 incrementing edge........................................ 157 two speed start-up .................................................... 51 usart synchronous receive (master/slave) ......... 338 usart synchronous transmission (master/slave) . 338 wake-up from interrupt ............................................... 80 timing diagrams and specifications pll clock.................................................................. 329 timing parameter symbology........................................... 327 timing requirements i 2 c bus data............................................................. 343 spi mode .................................................................. 341 tmr0 register.................................................................... 22 tmr1h register ................................................................. 22 tmr1l register.................................................................. 22 tmr2 register.................................................................... 22 tris.................................................................................. 312 trisa register........................................................... 22, 105 two-speed clock start-up mode........................................ 50 txreg ............................................................................. 259 txreg register ................................................................. 23 txsta register.......................................................... 23, 267 brgh bit .................................................................. 270 u usart synchronous master mode requirements, synchronous receive .............. 338 requirements, synchronous transmission...... 338 timing diagram, synchronous receive ........... 338 timing diagram, synchronous transmission... 338 v v ref . s ee adc reference voltage vregcon register ........................................................... 82 w wake-up on break ............................................................ 276 wake-up using interrupts ................................................... 80 watchdog timer (wdt)...................................................... 64 associated registers .................................................. 86 configuration word w/ watchdog timer..................... 86 modes......................................................................... 84 specifications ........................................................... 332 wcol ....................................................... 234, 237, 239, 241 wcol status flag.................................... 234, 237, 239, 241 wdtcon register ............................................................. 85 wpub register................................................................. 107 write protection .................................................................. 37 www address ................................................................. 405 www, on-line support ................................................... 2, 5
? 2011-2012 microchip technology inc. ds41441c-page 405 pic12(l)f1840 the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notification? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support
pic12(l)f1840 ds41441c-page 406 ? 2011-2012 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip product. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to: technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds41441c pic12(l)f1840 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2011-2012 microchip technology inc. ds41441c-page 407 pic12(l)f1840 product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx xxx pattern package temperature range device device: pic12f1840, pic12lf1840 tape and reel option: blank = standard packaging (tube or tray) t = tape and reel (1) temperature range: i= -40 ? c to +85 ? c(industrial) e= -40 ? c to +125 ? c (extended) package: (2) mf = micro lead frame (dfn) 3x3 p=plastic dip sn = soic, 8-lead pattern: qtp, sqtp, code or special requirements (blank otherwise) examples: a) pic12f1840t - i/mf 301 tape and reel, industrial temperature, dfn package, qtp pattern #301 b) pic12f1840 - i/p industrial temperature pdip package c) pic12f1840 - e/sn extended temperature, soic package note 1: tape and reel identifier only appears in the catalog part number description. this identifier is used for ordering purposes and is not printed on the device package. check with your microchip sales office for package availability with the tape and reel option. 2: small form-factor packaging options may be available. please check www.microchip.com/packaging for small- form factor package availability, or contact your local sales office. [x] (1) tape and reel option -
? 2011-2012 microchip technology inc. ds41441c-page 408 pic12(l)f1840 notes:
? 2011-2012 microchip technology inc. ds41441c-page 409 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, k e l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, application maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. & kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2011-2012, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 9781620768105 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal me thods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outsi de the operating specifications c ontained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
ds41441c-page 410 ? 2011-2012 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://www.microchip.com/ support web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 indianapolis noblesville, in tel: 317-773-8323 fax: 317-773-5453 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8569-7000 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - chongqing tel: 86-23-8980-9588 fax: 86-23-8980-9500 china - hangzhou tel: 86-571-2819-3187 fax: 86-571-2819-3189 china - hong kong sar tel: 852-2943-5100 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8864-2200 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 asia/pacific india - bangalore tel: 91-80-3090-4444 fax: 91-80-3090-4123 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - osaka tel: 81-6-6152-7160 fax: 81-6-6152-9310 japan - tokyo tel: 81-3-6880- 3770 fax: 81-3-6880-3771 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-5778-366 fax: 886-3-5770-955 taiwan - kaohsiung tel: 886-7-213-7828 fax: 886-7-330-9305 taiwan - taipei tel: 886-2-2508-8600 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 worldwide sales and service 11/29/12

▲Up To Search▲

Price & Availability of PIC12F184012

	To Download PIC12F184012 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .